I was writing my code for non restoring division algorithm in VHDL and experiencing some problem, in the code I have written 16 bit division, but while doing synthesis waveform I didn't get the correct result code is shown below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity division is
Port ( q : in STD_LOGIC_VECTOR (15 downto 0);
m : in STD_LOGIC_VECTOR (15 downto 0);
qf : out STD_LOGIC_VECTOR (15 downto 0);
rf : out STD_LOGIC_VECTOR (15 downto 0);
clk:in std_logic;
rst:in std_logic);
end division;
architecture Behavioral of division is
signal aq,m_sub,m_add:STD_LOGIC_VECTOR (32 downto 0);
signal m_neg: STD_LOGIC_VECTOR (16 downto 0);
signal count:std_logic_vector(4 downto 0);
begin
m_neg<=(not('0'&m))+1;
process(clk,rst,m)
begin
if(rst='1') then
count<="00000";
aq<="00000000000000000"&q;
m_add<='0'&m&"0000000000000000";
m_sum<=m_neg&"0000000000000000";
elsif rising_edge(clk) then
count<= count+"00001";
if(count<="1111") then
aq<=aq(31 downto 0)&'0';
if(aq(32)='1') then
aq<=aq+m_add;
else
aq<=aq+m_sub;
end if;
aq(0)<= not(aq(32));
elsif(count="10000") then
if(aq(32)='1') then
aq<=aq+m_sum;
else
aq<=aq+m_sub;
end if;
else 
aq<=aq;
end if; 
end if;
 
qf<=aq(15 downto 0);
rf<=aq(31 downto 16); 
end process;
end Behavioral;

 

How about showing some test waveforms comparing what you applied, what you got, and what you consider to be the correct waveform that you were expecting to see?

 

---------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY vtest_vhd IS
END vtest_vhd;
ARCHITECTURE behavior OF vtest_vhd IS 
 -- Component Declaration for the Unit Under Test (UUT)
 COMPONENT division
 PORT(
  q : IN std_logic_vector(15 downto 0);
  m : IN std_logic_vector(15 downto 0);
  clk : IN std_logic;
  rst : IN std_logic;          
  qf : OUT std_logic_vector(15 downto 0);
  rf : OUT std_logic_vector(15 downto 0)
  );
 END COMPONENT;
 --Inputs
 SIGNAL clk :  std_logic := '0';
 SIGNAL rst :  std_logic := '0';
 SIGNAL q :  std_logic_vector(15 downto 0) := (others=>'0');
 SIGNAL m :  std_logic_vector(15 downto 0) := (others=>'0');
 --Outputs
 SIGNAL qf :  std_logic_vector(15 downto 0);
 SIGNAL rf :  std_logic_vector(15 downto 0);
BEGIN
 -- Instantiate the Unit Under Test (UUT)
 uut: division PORT MAP(
  q => q,
  m => m,
  qf => qf,
  rf => rf,
  clk => clk,
  rst => rst
 );
 tb : PROCESS
 BEGIN
  -- Wait 100 ns for global reset to finish
  wait for 100 ns;
  
rst<='1';
wait for 100 ns;
rst<='0';
q<=x"0008";
m<=x"0003";  -- Place stimulus here

  wait; -- will wait forever
 END PROCESS;
process
begin
clk<='0';
wait for 5 ns;
clk<='1';
wait for 5 ns;
end process;

END;

 

Above code is for division of 8 by 3, and below I've shown waveform where;
m_reen > m_add
m_dhan > m_sum

Sir pls provide me ure email id, there is a problem posting image file on this website

 

Above code is for division of 8 by 3, and below I've shown waveform where;
m_reen > m_add
m_dhan > m_sum

Sir pls provide me ure email id, there is a problem posting image file on this website

Everyone else posts image files all the time. Be sure you are following the guidelines for posting image files.

And, no, I most certainly will NOT provide you with my e-mail address.

 

https://picasaweb.google.com/110000179370472412937/Query#5890713695716044706

 

I am performing here division of 8 by 3. And result should be 2 remainder and 2 quotient, whereas in the test bench waveform I've got something wrong.
here "qf" is final quotient and "rf" is final remainder in which result is kept

 

What is your division algorithm supposed to be doing? I see lots of shifting and adding, but not familiar with that method. Also hard to read your code w/o indentations.

 

An interesting read on restoring and nonrestoring division algorithms.

http://www.stanford.edu/class/ee486/doc/chap5.pdf