here you go SgtWookie.. i have attached a hand drawn copy of the circuit, hope this would be better to understand...

In the circuit diagram, the output of the transistor (Vadj) should go to pin 13(V0) and not pin 10 of the LCD; apologies

 

@marshallf3, we duplicated the effect of heat, when we blowed a hair dryer to it... But again, it was not everytime, that the temperature affected the performance of the circuit, 2 days before, we had everything constant, temp of room was steady at 72°F, but still there was a change in the output voltage across the transistor..

Although heat is the most common place to start with an intermittent some things are just intermittent at random.

Have you looked closely at all the solder connections on the board?

I've got to leave, can someone post some example pictures of cold solder connections?

 

there are 100's of such boards, and its not that every board has the same problem, its only that 10/100 have this weird problem...

 

It appears from the datasheet in table 5.1 that the recommended driving voltage for V0 is -20V to -22V, relative to VDD. If VDD=+5V, that would make the recommended V0 range -15V to -17V.
If VDD=+3.3V, the recommended V0 is -16.7V to -18.7V.

Assuming the transistor Vbe=0.7V, your adjustment range is approximately -17.4V to -19.1V.

According to the datasheet, V0 is on pin 13. You show Vadj going to pin 10, which is VDD. Is that an error on your schematic?

 

Ron, I am extremely sorry for the schematic, the Vadj of the transistor should go to pin 13, V0 and not pin 10...

I am extremely sorry for the confusion...

Also, I would like to add some more points, the output of the transistor(Vadj) is typically is between -15V to -20V; and the Vdd is +5V;

so that (Vdd - V0) is in the range of 20V to 25V

 

Well, the voltage on pin 13 would then be very dependent on the gain of the individual PNP transistor over temperature. This will likely vary widely, as transistors in any given batch have different "personalities".

One way to fix it would be instead of using the PNP transistor, use an opamp with a gain of around 4.

 

hmm.. but do you think problem would be the transistor and not zener diode or the digital pot???

 

Why don't you heat some of the units up until they malfunction, measure the temperature, and use a chiller spray like what was previously suggested to find out which component is the cause of the problem?

 

Well, the voltage on pin 13 would then be very dependent on the gain of the individual PNP transistor over temperature. This will likely vary widely, as transistors in any given batch have different "personalities".

One way to fix it would be instead of using the PNP transistor, use an opamp with a gain of around 4.

Emitter follower gain is very close to unity. As long as beta is high (>100, arbitrarily), the gain will be pretty much independent of the individual transistor selection.

 

Ron, I am extremely sorry for the schematic, the Vadj of the transistor should go to pin 13, V0 and not pin 10...

I am extremely sorry for the confusion...

Also, I would like to add some more points, the output of the transistor(Vadj) is typically is between -15V to -20V; and the Vdd is +5V;

so that (Vdd - V0) is in the range of 20V to 25V

According to your schematic, your total adjustment range is only about 2.2V. Perhaps you have drawn the schematic incorrectly. Are you sure of the placement of the 7.5k and the 15k resistors?

 

Thanks Ron, you're right - I kept getting confused by the way the schematic was drawn.

Here's basically the same thing, but with the transistor flipped around.
It's also in .PNG format so no software is needed.

 

Ron_H,

I threw together this simplified LTSpice simulation of CrackJack's circuit, just to see what kind of variation over temp one might get with that Zener and that 2N2906 transistor. Don't know the load current of the LCD panel offhand, so I just threw in a 22k resistor. Instead of going to the trouble of attempting to model the digital pot, I just used a plain 10k pot model.

Found a model for a 6.8v Zener in the same series; I changed a couple of parms to get it (maybe?) close to what their 5.1v Zener might be.

There's only about 2.39v of adjustment range in total. The voltage variation seems to be caused much more by the transistor than the Zener.

On top of this, there are likely variations in the Vdd (5v) supply, and as I mentioned, no simulation of the possible digital pot variations.

Anyway, it's a start.