hello, i wish to design a 100 input priority checker using ten 10-line-4 line priority encoder (ic 74147) by cascading them.the output has to be displayed using 2-seven segment displays.This will thus enable me to display the highest priority input which is low as ic 74147 is an active low input chip.For eg if out of 0-99 inputs,85th input input is low..the seven segment display must display 85.please help me with the circuit of combining the cascaded priority encoders and the 7-segment display.

 

The 74147 is a very poor choice for this task. Each IC will have the means of selecting the priority of inputs, but then there is no way to determine which of the '147's had the priority input first.

Look at the data sheet for the 74148 - it is made with cascading in mind.

 

well sir,74148 is a 8-3 decoder,the output being in octal code.i want to display the output in decimal form using two seven segment displays..thus,if i HAPPEN TO USE 100/8=13 priority encoders,what subsequent circuitry will help me to interface with the seven segment displays.?

cascaded priority encoders========seven segment displays(msb)
=========seven segment display(lsb)

 

Part of the purpose of priority encoding is to display the first input to go low. A 74147 can do that for any of its 10 inputs, but lacks the means of cascading out to more priority encoders.

The 74147 lacks a disable input, so the priority display logic would need external logic to prevent being overridden by another input to a different 74147.

The 74148 presents the problem of converting octal to BCD - the 74147 has to have a certain amount of extra logic to insure the display is of the one input with priority. It's an interesting problem with either approach.

 

Octal to 7 Segment could be done through a small (20 pin) PAL, such as the ATF16V8C

If you are at the level of programming a PAL, a bit of a step, your entire project could be implemented on a single high pin count, but relatively low cell count CPLD or FPGA.

To handle over 100 inputs to seven segments using standard logic ICs would require a much more complex PCB, large number devices, and very difficult to correct bugs.

I usually don't suggest "high end" solutions like this, as the PCB typically need to be made at a fabhouse when dealing with such high pin densities, but it would be the overall lowest cost, and quickest route to a functional device.

--ETA: This could also be done with half a dozen or so PALs, if the code provided for cascading enough to handle the inputs, giving a 4 bit output, and one for prioritizing the others and managing the display.