Power supply theory Question

Thread Starter


Joined Apr 12, 2007
Dear All,

I have the attached power supply circuit, but i don't know the function of the op-amp U1, U2, and U3.
Did any one can tell me!

Thank you all very much!




Joined Apr 2, 2007
The attachment is corrupted. Can you check it and try uploading again?
no, its not.
u'll need support for Japanese fonts sir.
i have those so i was able to see the file.

arent Chinese and Japanese scripts same?
kanji, hiragana, etc(those in my avatar)

watashi no 'offtopic post' kara, sumimasen deshita!:D



Joined Sep 21, 2007
The circuit is poorly designed. It is practically a mess. I think U1 is a voltage reference, but I'm not sure.
How can you say it is a poorly designed mess when you admit you do not really understand it? Is it not possible that the circuit is more complex than you would expect it because it has better performance than a simpler circuit? I would not be so quick to dismiss something I do not understand.

A quick glance seems to show U1 is a very stable voltage reference, much more stable than just a zener diode. U2 is the voltage controller and U3 is the current controller. D5, D6, D7 etc create a negative bias voltage.

Being unable to read Chinese I have no idea of the text that goes with it but the design seems reasonable to me.

What exactly is so wrong about it?

Ron H

Joined Apr 14, 2005
U1, D8, R4, R5, and R6 form a self-biased zener reference. The output voltage is only as stable as these parts are. The main feature of this circuit is that the zener bias current has no supply ripple, as it would have if it were biased off the unregulated supply. The output voltage is equal to 2*Vz, or 11.2V nominal, in this case.
U2 is the error amplifier, setting the output voltage to approximately 3 (1+R12/R11) times the voltage on the wiper of P1.
U3 is the current limit comparator. The output current flowing through R7 creates a negative voltage on the lower end of R17. If the resulting current through R18, P2, R17 causes the wiper of P2 to go below ground, which is the reference for the inverting input of U3, then the output of U3 will go low enough to cause D9 to conduct, which pulls down on the reference voltage into U1. This is a (presumably stable) negative feedback loop which clamps the output voltage so that the current is limited to the level set by P2.
If the output current is grossly over limit (i.e., shorted), Q1 will conduct very rapidly, turning off and protecting the output series pass transistor.
I can't see any glaring poor design practices here.