International Rectifier's datasheet says "Logic inputs are compatible with standard CMOS or LSTTL output, down to 3.3V logic."
My interpetation is that for Vdd = 5V the input low/high logic transition occurs around Vdd/2 = 2.5V ± about 5% of Vdd, allowing for the input Schmitt hysteresis. Thus the logic high threshold would be 2.75V, so 3.3V from the MCU in theory would be treated as logic high, but the noise margin would be reduced.
Why can't you use 3.3V as the Vdd?