When I was asking here some time ago on how to properly 'line up' two 2732s to replace them with a 2764, it was suggested that I tie the ~CE line to ground.
I just realized... wouldn't that cause bus contention issues?
Should I have tied that line to the master clock instead?
Every other major IC on the two logic boards has an enable line tied to the master clock.
Link to old thread
I just realized... wouldn't that cause bus contention issues?
Should I have tied that line to the master clock instead?
Every other major IC on the two logic boards has an enable line tied to the master clock.
Link to old thread
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