Hi all,
I'm getting an incorrect result upon passing a positive pulse train through a capacitor in LTSpice (see attached screendump). These particular pulses are 0 - 100mV 10uSec pulses (pulse frequency 10 KHz, 10% dutycycle). The pulses retain their 0 to 100mV polarity even after passing through the capacitor. Changing the frequency, or the dutycycle, or the capacitance makes no difference to this anomaly. A positive sine wave Independent voltage Source (ranging from 0v to Fv where F>0), does correctly change its polarity to -0.5Fv to +0.5Fv when passed through a capacitor, but apparently not the Pulse. What am I doing wrong?
(PS I tried a number of times to upload a screendump of the LTSpice page with the circuit and simulation output but I got the error message "There was a problem uploading your file". I tried with both .jpg & .gif versions - same error msg.)
I'm getting an incorrect result upon passing a positive pulse train through a capacitor in LTSpice (see attached screendump). These particular pulses are 0 - 100mV 10uSec pulses (pulse frequency 10 KHz, 10% dutycycle). The pulses retain their 0 to 100mV polarity even after passing through the capacitor. Changing the frequency, or the dutycycle, or the capacitance makes no difference to this anomaly. A positive sine wave Independent voltage Source (ranging from 0v to Fv where F>0), does correctly change its polarity to -0.5Fv to +0.5Fv when passed through a capacitor, but apparently not the Pulse. What am I doing wrong?
(PS I tried a number of times to upload a screendump of the LTSpice page with the circuit and simulation output but I got the error message "There was a problem uploading your file". I tried with both .jpg & .gif versions - same error msg.)