Hi all, As part of a uni assignment, we have to design a amp using NPN transistor 2N3904, PNP transistor 2N3906 and a p-channel JFET 2N5460. The idea is to create an amp with the largest gain-bandwidth product, in the form |Av|*(F(h)-F(l)). The circuit is driven off of a 1mv/10kOhm source, with separate 12v/-12v rails and will be driving a 15 Ohm load. The JFET being what it is, it has a low bandwidth in common source and common drain configurations (around 2MHz, lower than the BJT's in CE which can still get 20-30MHz with lowish gain), so I was planning on using it as a common gate current follower in between the 2 BJTs, in a CE-CG-CC type fashion, with most of the gain on the CE (and a bit between the CG and CS). What I have been trying to do quiet unsuccessfully is essentially make a cascode out of a CE of one of the BJT's and the CG JFET (because of it's low input impedance). I can get reasonable gain with the CE, and reasonable with the CG, but I can't figure out how I can stick the 2 together to get a cascode with gain across both transistors. My biggest problem in trying to do the 'classic' cascode that you see with 2 NPN's is it is difficult to properly bias both the FET and the BJT together, as the FET only wants about 3mA bias which is quiet low for the BJT, so I end up with almost the full 24v drop across the FET which means the Vcb of the BJT can't be reverse biased. Also finding wrapping my head around the P-channel/N-channel and PNP/NPN differences quiet tricky. Am I barking up the wrong tree? Should I be rethinking my topology? I can't help feeling that in pursuit of and extra *10 bandwidth I'm going to rob myself of *30 gain or some such thing. There is little point bothering with a cascode out of the 2 BJT's if the FET is then going to be in CD/CS (and with a PNP/NPN I don't need to worry about the bias voltage stacking accross the stages), so maybe the best bet is to go CD-CE-CC for the extra input impedance (but doesn't a CE need lowish load impedance to get reasonable bandwidth? The high input impedance from the CC stage would cause large base/collector swings for the miller effect wouldn't it?). I can't use the FET last because maximum current I can draw from it is only about 3mA so would be totally unable to get a decent voltage across the 15 Ohm load. I'll try a CC-CG-CC configuration next, in my thinking that should give good gain on each stage without loosing to much bandwidth I haven't posted circuits because the individual stages are pretty standardized and being fiddled with anyway, and the combined doesn't work so not much point there either.