Hi all,

As part of a uni assignment, we have to design a amp using NPN transistor 2N3904, PNP transistor 2N3906 and a p-channel JFET 2N5460. The idea is to create an amp with the largest gain-bandwidth product, in the form |Av|*(F(h)-F(l)). The circuit is driven off of a 1mv/10kOhm source, with separate 12v/-12v rails and will be driving a 15 Ohm load.

The JFET being what it is, it has a low bandwidth in common source and common drain configurations (around 2MHz, lower than the BJT's in CE which can still get 20-30MHz with lowish gain), so I was planning on using it as a common gate current follower in between the 2 BJTs, in a CE-CG-CC type fashion, with most of the gain on the CE (and a bit between the CG and CS).

What I have been trying to do quiet unsuccessfully is essentially make a cascode out of a CE of one of the BJT's and the CG JFET (because of it's low input impedance). I can get reasonable gain with the CE, and reasonable with the CG, but I can't figure out how I can stick the 2 together to get a cascode with gain across both transistors.

My biggest problem in trying to do the 'classic' cascode that you see with 2 NPN's is it is difficult to properly bias both the FET and the BJT together, as the FET only wants about 3mA bias which is quiet low for the BJT, so I end up with almost the full 24v drop across the FET which means the Vcb of the BJT can't be reverse biased.


Also finding wrapping my head around the P-channel/N-channel and PNP/NPN differences quiet tricky.

Am I barking up the wrong tree? Should I be rethinking my topology? I can't help feeling that in pursuit of and extra *10 bandwidth I'm going to rob myself of *30 gain or some such thing. There is little point bothering with a cascode out of the 2 BJT's if the FET is then going to be in CD/CS (and with a PNP/NPN I don't need to worry about the bias voltage stacking accross the stages), so maybe the best bet is to go CD-CE-CC for the extra input impedance (but doesn't a CE need lowish load impedance to get reasonable bandwidth? The high input impedance from the CC stage would cause large base/collector swings for the miller effect wouldn't it?). I can't use the FET last because maximum current I can draw from it is only about 3mA so would be totally unable to get a decent voltage across the 15 Ohm load.

I'll try a CC-CG-CC configuration next, in my thinking that should give good gain on each stage without loosing to much bandwidth

I haven't posted circuits because the individual stages are pretty standardized and being fiddled with anyway, and the combined doesn't work so not much point there either.

 

Maybe you could try one of this topologies

Or if this diagram are to complicated for you I think you could start with classic CS - CE - CC configuration.

 

Thanks for that, looks like you put some time into them and I appreciate it

I'll sim the first, since it's fairly similar to something I tried earlier, though the cap from the PNP to Vcc has me puzzled. Also, why does the gate on the FET need biasing from Vcc? With a suitable resistor on the source of the FET couldn't you just run Vin straight from Vcc to the gate without a cap?

 

though the cap from the PNP to Vcc has me puzzled.

It's a bypass capacitor and if you confuse connect negative terminal to GND and positive to base of a PNP.

Also, why does the gate on the FET need biasing from Vcc? With a suitable resistor on the source of the FET couldn't you just run Vin straight from Vcc to the gate without a cap?

With the voltage divider in the gate we have more freedom in choosing Vgs then in the auto bais circuit.
But if you want to use auto bais without a cap you need voltage on the gate to be equal GND.

 

It's a bypass capacitor and if you confuse connect negative terminal to GND and positive to base of a PNP.

I'm familiar with polarised caps more about what it does; in the simulator it doesn't change the gains except at high frequency where the G/S capacitance on the FET starts happening. I can't see the benefit of putting the base of the PNP to AC ground or more to the point why it doesn't seem to have an effect on the mid band gains. I guess I need to study the small signal model better.

With the voltage divider in the gate we have more freedom in choosing Vgs then in the auto bais circuit.
But if you want to use auto bais without a cap you need voltage on the gate to be equal GND.

With the Vgs selection divider it lowers the input impedance substantially (a problem since the Vin has a 10kΩ internal resistance). I found with Vcc -> Vin -> gate and a small resistor on the source of the FET to select a suitable bias Vs for Vgs it works well.

The first which looks like a cascode with a voltage follower (which is what I was trying to make from the start) gets a smidge under 12dB with a cut off of 3MHz with the right resistors which I'm happy with. I'm guessing it's not worth trying to get a higher bandwidth with a non-differential power amp which needs a large load coupling capacitor like this as outside the simulator it would not pass much current at higher frequencies anyway.

In terms of the second - I haven't dealt much with feedback, and I don't have the time to learn it now so I can't use that without wholesale lifting it, which I'm not happy doing.

Thanks for the help