PMOS Transistor - Enhancement or Depletion Mode Device?

Thread Starter


Joined Mar 18, 2008
Hello, I am having trouble on a homework problem. I mainly need help in determing (a). Once I can get on track for part (a), the remaining parts should follow. I am thinking that V_TP will depend on the specific values of the resistors. How can I work through this problem mathematically?

Here is the problem:

The PMOS transistor in the circuit below is conducting.

(a) Is V_TP > 0 or V_TP < 0 for this transistor?
(b) Based on this value of V_TP, what type of transistor is in the circuit?
(c) Is the proper symbol used in the circuit?
(d) If the symbol is incorrect, which symbol should be used?

Here is the circuit:

Here are transistor symbols in my textbook:

Here are PMOS transistor equations given in my textbook:



Joined May 16, 2005
Vtp is an intrinsic property of the MOS. It does not rely on external components. Whether it is positive or negative depends on the type of MOS.

Connecting Body to positive will either provide more holes to a P substrate in a PMOS (moving Vtp closer to 0V), or suck electrons out of an N substrate in an NMOS (moving Vtp farther from 0V). Out here in the real world, Body is almost always connected directly to Source and we read Vtp from the datasheet.

The questions regarding whether the proper symbol is used, and what type of transistor is really in the circuit, are... well... stupid. Bad professor! No donut!


Joined Mar 1, 2007
lol :)
the professor needs more donuts alright :D

the fact that the transistor is conducting gives the clue:

assuming r1 = r2, gate is at half vdd.
assuming r3 = r4 and high enough, d and s terminals are at half vdd too.
for the pmos to stay conducting, it has to be a depletion one.

the symbol is an enhancement pmos, therefore, the symbol is wrong, it should be the symbol of a depletion one.

the v_tp is plus ( >0 ) for an depletion pmos.


Joined Mar 1, 2007
we're assuming the worst case. when in all conditions the terms are met, he couldn't be wrong in the answer.

assuming the pmos is an enhanced one and having to meet the condition that it is conducting, can be true only when the gate voltage is lower than the source.
so the assumption can't withstand all conditions, such as when the gate voltage is chosen to be near or equal vdd (r2=0). and lots of other combinations.