# PMOS CMOS strong 1 0 problem

#### nearownkira

Joined Feb 19, 2008
20
I have some problem regarding the strong or weak "1" "0" problem.

the reason why PMOS produce weak 0, because the PMOS wil turn off at some point.

the problem I dont know why PMOS will turn off like some point, not like NMOS will pull the voltage down to 0.

#### Dave

Joined Nov 17, 2003
6,970
The important aspect to note here is the threshold voltage ($$V_{th})$$of the transistor, which describes the voltage at which the transistor switches on and off (the on/off action of the transistor corresponds to the existence of the conducting transistor channel).

We know for nMOS transistors that the transistor is OFF when:

$$V_{gs}$$ < $$V_{th}$$

If $$V_{gs}$$ > $$V_{th}$$ then the nMOS transistor is ON.

For the pMOS transistor the voltages are expressed as negatives with respect to the nMOS voltage because of the opposing majority charge carriers in nMOS and pMOS transistors.

Therefore, for pMOS transistors the transistor is OFF when:

$$V_{gs}$$ > $$V_{th}$$

However in pMOS calculations $$V_{gs}$$ and $$V_{th}$$ will be negative voltages. You can take the magnitudes and the rules for pMOS transistors will be the same as for nMOS; therefore for pMOS transistors the transistor is OFF when:

$$|V_{gs}|$$ < $$|V_{th}|$$

Ok, so now we've cleared up the terminology and defined the above equations defining the switch on/off points consider a simple pMOS transistor (see attachment labelled with INPUT (Source), and OUTPUT (Drain)) with a voltage on the gate of 0 volts (a strong logic '0').

If the input is at $$V_{dd}$$ (a strong logic '1') which would be greater in magnitude than 0 volts, then:

$$|V_{gs}|$$ = $$|V_{dd}|$$ > $$|V_{th}|$$

The transistor will be switched on, and the input at $$V_{dd}$$ will be reflected at the output also as $$V_{dd}$$, i.e. the output will be a strong logic '1'.

This illustrates the strong logic '1' output for a pMOS transistor.

Ok, lets look at the case for logic '0'.

If we start to reduce the input voltage from $$V_{dd}$$ to 0 volts, we get to a point where the input voltage will equal $$V_{th}$$.

When the input gets to $$V_{th}$$, then:

$$|V_{gs}|$$ = $$|V_{th}|$$

And the transistor switches off - the conducting channel between the source and drain closes. At this point the voltage at the output is also $$V_{th}$$

Any further reductions in the input voltage will have no effect on the output voltage because the transistor is switched of by virtue of the fact that $$|V_{gs}|$$ < $$|V_{th}|$$

This illustrates the weak logic '0' of the pMOS transistor - that is the output can never get down to 0 volts (the point of a strong logic '0') because the transistor switches off before the output can get that low.

Dave

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#### nearownkira

Joined Feb 19, 2008
20
Any further reductions in the input voltage will have no effect on the output voltage because the transistor is switched of by virtue of the fact that $$|V_{gs}|$$ < $$|V_{th}|$$

This illustrates the weak logic '0' of the pMOS transistor - that is the output can never get down to 0 volts (the point of a strong logic '0') because the transistor switches off before the output can get that low.

Dave

thanks for the explanation.

It is the last part I dont understand, why further reduction in input voltage will not have any reduction in output voltage.

When Vgs less than Vth, it is CUTOFF and current is zero flowing between channel, how can there be voltage?

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#### Dave

Joined Nov 17, 2003
6,970
thanks for the explanation.

It is the last part I dont understand, why further reduction in input voltage will not have any reduction in output voltage.

When Vgs less than Vth, it is CUTOFF and current is zero flowing between channel, how can there be voltage?
The voltage on the output exists and is maintained at Vth because in real applications these transistors would be driving capacitive loads; for example if the transistors were a part of a cascaded set of CMOS logic gates, the pMOS drain (OUTPUT in the above attachment) would be driving the gate (a capacitor) of the next set of logic gates.

When the input drops below Vth, the transistor turns off, but the output voltage is maintained at Vth because of the voltage on the capacitive load - Vth is greater than 0V (a strong logic '0') and hence is described as a weak logic '0'.

See attachment.

The current through the transistor is due to Vds, but is superfluous to our considerations when the transistor is off. Electrostatic considerations mean we can have a voltage on the capacitive load in the absence of a current through the transistor (Consider the behaviour of a series RC circuit which is analogous to this transistor-capacitor arrangement in the attachment http://www.allaboutcircuits.com/vol_2/chpt_4/3.html).

Dave

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