Hello,

I'm trying to make a simple circuit that will emulate a load. This load has a power consumption in standby mode which is resistor R1. The parallel combination of R1 and R2 consume power as if the load is in operation.

The problem I'm having is trying to get the pmos to act as a switch and connect the two resistors.

The gate is connected to a microcontroller logic pin with a +5v high output.

3.7 volts is on a powerboard.

The ground of the powerboard and microcontroller are connected.

The following is a schematic of what I have so far.


My thoughts are that the gate voltage is floating and it never drops to 0V when the logic level is low. Possibly gate capacitance too.

Any help is greatly appreciated. Thanks.

 

What current do you want to switch? The IRF9530 is not a logic level MOSFET. Although it's maximum gate threshold voltage is -4V it is not suitable for this application.

 

The standby current is 60mA. The operating current average 675mA but can reach up to 1200mA.

Thanks praondevou.

 

How about this one?

http://search.digikey.com/us/en/products/IRLML2246TRPBF/IRLML2246TRPBFCT-ND/2639576

The output pin of the uC should go to almost 0V and 5V, meaning you have -3.7V Vgs to turn the MOSFET on and 1.3V to turn it off. Should be ok.

It will have an RdsON of about 100mOhm.

 

If R1 is grounded as shown, then how do you expect to "connect the two resistors"?

You schematic transistor icon has the drain and source interchanged (the labels are incorrect).

 

You schematic transistor icon has the drain and source interchanged (the labels are incorrect).

Good observation.

 

Crutschow,

I was thinking that when the pmos is on, R2+Rds(on) will be in parallel with R1. Is this correct?

Thanks for point that out on the schematic.

Praondevou your suggesting looks good to me except I'm looking for something that is through hole.

Thank you again.

 

Crutschow,

I was thinking that when the pmos is on, R2+Rds(on) will be in parallel with R1. Is this correct?

...............

Yes, when the transistor is on then R2 is in parallel with R1 from the power supply to ground. But, of course, the switching of R2 has no effect on the current through R1.

 

Crutschow,

Why does the principle of current division not apply here during switching?

I(R1) = (R2+Rds(on))*I/(R1+R2+Rds(on))


I'm actually not concerned with the current through R1 when the pmos is switched on but simply the total current being drawn.

If R2<<R1 there should be an increase in total current?

Thanks.

 

Crutschow,

Why does the principle of current division not apply here during switching?

I(R1) = (R2+Rds(on))*I/(R1+R2+Rds(on))


I'm actually not concerned with the current through R1 when the pmos is switched on but simply the total current being drawn.

If R2<<R1 there should be an increase in total current?

Thanks.

Yes the total current will increase due to turning R2 on. I just wanted to make the (obvious) point that the current through R1 is a constant, independent of R2. Sorry if I confused you with that.

 

I'm not sure what you mean about current being independent.

If R2 is in parallel with R1 (when pmos is on) that would make the current value I(R1) dependent on R2+Rds(on) due to current division. Yah?

Thanks.

 

I'm not sure what you mean about current being independent.

If R2 is in parallel with R1 (when pmos is on) that would make the current value I(R1) dependent on R2+Rds(on) due to current division. Yah?

Thanks.

Not if Vdd is fixed at 3.7V: if this is so I(R1) = 3.7V/R1 at all times.

Current division would affect I(R1) only if the total current from the Vdd supply were constrained in some way, say by a limiter so that Vdd was reduced as I(R2) increased.

Is the Vdd supply a fixed voltage or not?

 

I was confusing myself for some time. I got it thanks.