Is it possible to determine the phase error of a PLL in steady state knowing only:

- open loop dc gain value (kv)
- vco gain (kd)
- the phase detector is a 4 quadrant multiplier

 

Have you read this ..... ?

http://www.national.com/an/AN/AN-46.pdf

 

Thank you for your answer.
I will take a look at this file =)