- Joined Mar 12, 2011
I am calculating that I am only getting 16MHz signal because when I implement a 4 instruction loop I get a frequency on PORTA of about 1MHz. I know each instruction takes 4 cycles so 4*4*1Mhz comes out to 16MHz. Yeah I can do math! Well I am trying to enable the PLL bit so I can multiple that signal by 4, creating a 64MHz monster signal. I have enabled the PLL bit by this instruction bsf OSCTUNE,6. I am still not getting the 64MHz signal though.
Rich (BB code):
CONFIG FOSC = INTIO7, FCMEN = OFF, IESO = ON, PWRT = OFF, BOREN = OFF CONFIG BORV = 18, WDTEN = OFF, WDTPS = 1, MCLRE = ON, HFOFST = ON CONFIG LPT1OSC = OFF, PBADEN = OFF, CCP2MX = PORTC, STVREN = OFF CONFIG LVP = OFF, XINST = OFF, CP0 = OFF, CP1 = OFF, CP2 = OFF CONFIG CP3 = OFF, CPB = OFF, CPD = OFF, WRT0 = OFF, WRT1 = OFF CONFIG WRT2 = OFF, WRT3 = OFF, WRTB = OFF, WRTC = OFF, WRTD = OFF CONFIG EBTR0 = OFF, EBTR1 = OFF, EBTR2 = OFF, EBTR3 = OFF CONFIG EBTRB = OFF START movlw 0x09 movwf PLCounter movlw 0x06 movwf ExtraCounter movlb B'00001111' clrf PORTA comf PORTA movlw 0xE0 ; Configure I/O movwf ANSEL ; for digital inputs movlw 0xC0 ; Value used to movwf TRISA ; Set RA<5:0> as outputs clrf OSCCON bsf OSCCON,1 bsf OSCCON,4 bsf OSCCON,5 bsf OSCCON,6 bsf OSCTUNE,6 movlw 0x10 ; start loading pixels at RAM location x10 movwf FSR0L,1 movlw 0x50 ; start loading pixels at RAM location x10 movwf FSR0H,1 Freq comf PORTA comf PORTA goto Freq END