Im in a test right now, and I need to write a VHDL program to implement in a CPLD a 5-digit BCD adder.
Im to assum that the following components in the design hierarchy have been implemented in .vhd files that are stored in the same directory as the program.
-- Full adder in full_add.vhd
-- 4-bit parallel adder in addpar4.vhd
-- single digit bcd adder in bcd_add.vhd
The program that I am creating just isnt working right,, If someone could paste a program so I can check mine that would be awesome!!
THANKS
Im to assum that the following components in the design hierarchy have been implemented in .vhd files that are stored in the same directory as the program.
-- Full adder in full_add.vhd
-- 4-bit parallel adder in addpar4.vhd
-- single digit bcd adder in bcd_add.vhd
The program that I am creating just isnt working right,, If someone could paste a program so I can check mine that would be awesome!!
THANKS
