Hello again,

Background: I started with one FET in a bridge. The FET was outdoors. I managed to get good signal strength, though it was usually very noisy, but the FET was too sensitive to temperature changes and this skewed my results.

I remade the circuit with 2 FETs in a differential amplifier circuit, and kept them indoors. One gate was still connected to the antenna outdoors, the other was grounded.. There was still a lot of noise but now my signal strength was as low as 1% of what I originally had with the single FET outdoors. Biasing was very difficult now.

I next moved the 2 FETs outdoors so both saw the same temperature changes. The rest of the circuit was unchanged. Now the signal is not noisy, but I did not get my sensitivity back. Bias settings which worked in the past no longer work. I've tried many variations and the results are either unstable (signal jumps around) or the sensitivity is extremely poor. Biasing is harder than ever now.

I tried biasing the antenna gate, but the voltages and currents I'm working with are so small that the signals get drained to ground. I get more signal if the one gate floats with the antenna. It worked in the past so I went back to it.

I need help biasing the 2 FETs in the bridge circuit shown here. I'm having an awful time getting useful signals.

The left pic is the typical diff amp layout. The right pic is redrawn to indicate the FETs outdoors.
I'm working with DC and trying to sense static electric fields.
Thanks for any help.

 

Can someone suggest some resistor values for bias? I've been working on this for weeks and have tried many combinations of source and drain resistances but nothing gives me a stable output with good gain, even when it looks ok in a simulated circuit.
I've tried using several formulas and "rules-of-thumb" found online such as:

Ideal Vd formula...
Vd = (((Vcc-Vs) / 2) + Vs)
..................................................
(Vcc – (Min Rds(on) * Ids)) / Ids = total resistance Rd + Rs
.................................................
setting Vd ~ = 1/2 supply V and Ids = 8 to 10
.................................................
Rd must be greater than twice Rs or the gain will be less than unity.
Vcc must be approximately greater than 4*|Vp| or the gain will be less than unity.
................................................
optimum drain voltage, which is dependent on supply voltage and Vp, can be approximated by
Vd = (0.6 * Vcc) + (0.7 * |Vp|)

The required drain resistor will be
Rd = 0.9 * ((Vcc - (2 * |Vp|))/ Idss)
and,
Vs = |Vp| * (((0.37 * Vcc) - (0.65 * |Vp|)) / (Vcc - (2 * |Vp|)))
.................................................................

... but nothing gives me decent results. At least some of these formulas are for audio amps which is not my use.

Furthermore, when running simulations, there seem to be many combinations of source and drain voltage values which can give apparently useful results.

To top it off, when I do the calculations and plug some variables into a simulation, I don't get the calculated results for the other variables.

In all cases, I can tweak the simulated circuits for better gm or voltage out vs voltage in and get better numbers than the formulas give me.

I don't know what to believe.

Below is a typical graph of my output...

I got this with these settings:
Rd1 = Rd2 = 3.02K ohms
Rc (Rs) = 347 ohms
Vd = 8.25 V
Vs = 4.71 V
Ids = 6.77 mA
a 1 mV input gave a 12.37 mV output in the simulation
Vcc = 24.7 V
"samples" are outputs taken at 1 second intervals.

I need some guidance here.
Thanks

 

I think I see what you're trying to do here.

Now, even with Rc set to max (i.e. 347 ohms), the "tail" current for the differential pair will be about 20mA, which means about 10mA for each transistor (assuming they're well-matched). This is too much current for the drain load resistors, so the transistors are fully on. For this to work at 20mA, you'd need to aim for a quiescent drain voltage of about 16V, so 820 ohm resistors would be about right.

Just scale these resistor values as you please, and you should be OK.

 

I've just had a look at the mpf102 datasheet, and I think you ought to abandon use of a single supply; for a differential pair to work properly I think you should add a negative supply (say -15V), try using a 15k tail resistor, which ought to yield just over 500uA per transistor (if they're well matched), and then use 12k drain load resistors (with a 5k pot for balancing).

Again, scale these resistor values as you please.

 

Thank you for your reply Hi-Z.

The antenna is sensing atmospheric charge as it varies slowly in a roughly sinusoidal pattern over 24 hrs. I'm specifically looking for changes during thunderstorms, but in the past the high noise levels and spikes from EMF due to lightning have swamped the part of the signal I want to see. I was never able to eliminate the noise or locate the source, but now, for some reason, the noise is tremedously reduced, though moving the FETs out to the antenna did not reclaim the kind of signal strength I used to have when I was using just 1 FET.

The FETs I'm using are not matched in any way. I know they really should be, but I didn't think it would be such a big factor because they are not being switched on and off, just varied in between by the slowly varying potentials sensed by the antenna. I thought that adjusting the bias for each FET individually to get 0 V bridge output would do something to balance their operation. Perhaps I was wrong.

It sounds like you're saying this is a much more important factor than I thought.

Perhaps I should mention that the way I've been choosing my resistor values is to start with some supposedly decent value, plug it into a simulation, then tweak the values while watching the amplitude of an output signal. I use a 1mV input signal and I've gotten output signals up to 81mV in the simulation. I then set my pots to match the simulation. I have no idea if this is a good way to do this or not, but it seems to give better results than anything else I've done.

I will look into trying to match the FETs before using them is the circuit, but for the time being I will try your suggestions. thanks.

 

Just to add a bit of explanation regarding what I've been saying:

In general, for a differential pair of jfets which has the "reference" input grounded, it's not particularly satisfactory for the "tail" of the pair to consist of a resistor to ground. Even if both fets are matched for Vgs, you'll need the Vgs at the particular fet current to be rather high. Looking at the mpf102, Vgs for 200uA can vary from -0.5V to -7.5V. Not bad if both fets have Vgs of -7.5V, as you won't get too much change in current as you take one input in the positive direction. Rather nasty if your fets have Vgs of -0.5V; you'll get a massive rise in current as one input is taken positive. Not only that, if your input voltages droop below ground, you'll rapidly run out of current.

You might just about be able to get away with a single supply if you have a current sink in the tail, instead of a resistor, but this is adding complication. If it's easy to add a negative supply, that would be the best solution, as it allows a high value resistor to be used to provide a relatively constant current whatever the inputs do.

The large range in the Vgs spec means that it'll be desirable for matching of the fets. Obviously, if there is a significant difference between transistors, this would manifest itself as an offset voltage at the input of the amplifier, so you might find a 7V differential input voltage resulted in zero differential output. However, as long as there is approximate matching, the balance pot in the drain circuit should be able to compensate.

I do notice that there is a danger in exceeding the maximum drain to gate voltage of 25V if the input is taken lower than about -4V (with my resistor values). That's because of the rather high 24.7V positive supply. Possibly this could be reduced (and you'd get reduced gain as you'd need to reduce the drain load resistor values). Or maybe consider use of different jfets?

Finally, one thing to look out for in the practical circuit is oscillation. These are quite high frequency devices, and they will probably be rather given to oscillating in differential-pair/source-follower type applications. It's caused by capacitance between source and ground, so keep this to a minimum! You can often fix it by adding a "gate-stopper" resistor of about 100 ohms in series with and physically close to the gates.

 

Thanks for the in-depth explanation.

First, the "bridge" absolutely needs to be grounded as it works as the input for an instrumentation amp when the DVM is not used. This amp needs a bias return path and the bridge can double as that path. Balancing the bridge to zero V is also necessary and easier than other ways to satisfy the in-amp.

Second, I do have a dual power supply which I use to run both the bridge and the amp. Bridge has been working at +15V/0V and the amp uses +/- 15 V with 0V as the reference. I only recently tried increasing the power supply voltage in an attempt to increase the gain. It worked in the simulation but not in real life.

Third, I try to keep capacitance between gate and ground to a minimum because even a few pF destroys the sensitivity of the circuit.

Also, although the reference input is grounded, it is still an input. If there is significant atmospheric charge, such as in the vicinity of a thunderstorm, the local ground potential will be opposite to the clouds. This provides a second input, opposite to what the antenna detects, thus giving a bigger signal. The antenna shown here is just half of the entire antenna. The grounded circuit with second FET is the other half.

As for the oscillation, in the past I've had extremely noisy output from the circuit which has not been reduced by any type of filter I could make or buy, or the use of decoupling caps or resistors. I don't know why my signal is so quiet now, but it isn't doing me much good with such low sensitivity. Amplifying a low sensitivity (low resolution) signal just gives me a bigger low resolution signal. My first circuit using one FET gave better sensitivity and resolution, it was just noisy. The 24 hr signal was almost 200 mV p-p and would vary on the order of minutes, not a few tenths of 1 mV over 6 hour blocks of time as I'm seeing now.

The 3 main problems I've seen have been 1- the single FET bridge had too much noise. 2- the double FET version has only a small fraction of the sensitivity of the single FET version (not what I expected). 3- Lightning causes huge spikes which no amount of filtering can eliminate and this, along with the basic noisy background, swamps the signal I'm looking for.
I don't seem to be able to solve any of these problems.

This started out as a very small, simple circuit which has grown in complexity over the last 2 years as I tried to make improvements and learned by trial and error experience and a lot of research. I still try to keep it as simple as I can - if I can't understand what is happening, I can't try to fix it. I really appreciate your explanations of what is going on, but even with 2 years of research on this project, some of what you said is new to me. It sounds like I'd be looking at another year of learning to familiarize myself with the details you pointed out and get the circuit into almost working condition again. I'm not prepared to put that much more time into this and I am very tempted to quit at this point. The circuit is almost doing what I'd hoped, sensing the presence of thunderclouds overhead, but I can't go any farther without more sensitivity.

 

I may be completely wrong for this circuit, but here goes:

dual fet circuits are balanced in the source circuit, not the drain circuit. Split supplies are obvious if your gates are referenced to zero volts. Dual, matched fets are available in a single package. Running a jfet with less than 1 volt from source to drain gets into problems with the fet never getting into operating range, that is, the idle current is dependent on the Vsd too much. It should depend solely on Vgs, and giving the fet enough Vsd allows that.

 

Hi #12,

I used to balance the circuit with a pot between the 2 sources (or the source resistors), and sometimes I still can, but lately I'm finding that any extra resistance in that part of the circuit just makes the bridge more unbalanced. Therefore I have no choice but to adjust one of the drain resistors. I figured it had to do with the FETs being badly matched or something similar.

I recently learned of matched FETs in a single pkg, but the prices I saw were something like $35 and this project is not worth it.

I just started a new test. These are the stats from the simulation and my measurements.

Vcc = +/- 15 V
Rd1 and 2 = 9,175 Ω
Rs = 0 Ω
Rc = 14,361 Ω
zero pot = 100 Ω
Vd = 8.02 V
Vs = 6.9 V
Ids = 761 uA
Vgs = 8.02 V
Vds = 1.12 V
sat
gm = 1.38 mA/V
signal in-out = 1 mV - 11.82 mV​

The 100 Ω zero pot is ineffective. I had to increase Rd2 a little again.​

I keep noticing that I'm getting the best amplification in the simulations when Vd is close to 8V. Vp for the MPF102 is -8V.
I usually try for an Ids up to about 12 mA. Rarely this low, but the output vs input looks decent, so I'm trying it.
Thanks.​

 

Digikey has 2 dual N-channel j-fets for under $1

Running the Vgs positive is so wrong that I can't even imagine how that works.
Even if the polarity is correct, -8 Vgs lowers the current to about 2 nanoamps.
I think you're Simmed yourself to death.

 

Oh dear, you're sounding very despondent - please don't give up just yet!

Regarding your latest simulation results (and I like the idea of a +/- 15V split supply), I would say that you've chosen the maximum possible values for Rd without running out of Vds, and no doubt the reason was to get maximum gain. The trouble is, there won't be much headroom here - any signal resulting in more than a few hundred mV at the output will result in clipping.

I think if you're straining for gain, you should try increasing the operating current a bit (by reducing Rc), and by reducing the Rd values by a somewhat greater amount (you ought to have a quiescent value of Vds of a few volts). And a 100 ohm pot won't be nearly enough in practice for zeroing the output (as you've found).

Having said that, the Vgs of -6.9V is right at the max end of the mpf102 spec. Are you measuring this in real life, or is it just a simulation result? If it's the latter, you may be pleasantly surprised when you try it on the bench with those resistor values. (Otherwise I think you'll need to reduce the Rd values, as I've explained.)

Regarding your previous post, I think the reason you've been experiencing a reduction in gain and noise is because, with your original resistor values, you were running too close to clipping. Was your single-transistor circuit a common-source type amplifier? It sounds like you need the differential circuit if the "ground" reference is bouncing up and down.

I've just realised your transistor sources (and drains) will be "seeing" a large capacitance to ground (and also to each other), owing to the screen of the shielded cable. This could be problematic in terms of causing oscillation - but if you're happy that you aren't getting this sort of problem (and note that it would be at a very high frequency), then just keep your fingers crossed!

Regarding the interference due to lightning, this sounds like a problem that'll be difficult to avoid. I would certainly minimise this by including diodes across the inputs (which I appreciate might be tricky to do), but spikes will still be amplified to a few volts. However, if your differential pair has sufficient headroom, you may well be able to cope with this using low-pass filtering - starting with a suitable capacitor at the diff amp's output (ie. connecting the two drains at high frequencies). Further filtering could be done downstream.

As I'm writing this I'm having further thoughts: is it really necessary for the transistors to be fairly local to the antennae? If not then you could get rid of the 25' shielded cable, the protection diodes would be much easier to implement and you wouldn't have a potentially problematic capacitance to worry about.

Anyway, please don't give up yet!

 

Oops, my mistake. I've been looking at the voltage and current values and ignoring the polarity because it has always been the same. These should be:
Ids = -761 uA
Vgs = -8.02 V
Vds = -1.12 V
(In reality I'm a chemist, not an electrical engineer, and we always learned that current flows from neg to pos, opposite to what they teach in electronics classes. I firmly believe electrons move and the positive wire ions stay put. I have seen electrons move, but I've never seen a wire crawl along a desktop. Therefore, I can be expected to measure polarity opposite to what others are used to.....Just kidding, I couldn't resist that. I've been waiting a long time to say that to someone.)

I have often wondered if I was doing just what you said "simmed myself to death." I've suspected that it's possible to gradually tweak a circuit into some temporary, good, but highly unstable configuration. This just adds to my dilemma of not knowing what to believe.

Thanks for the tip about Digikey. I'll definitely check it out.

 

I'm not saying a DC coupled jfet amplifier won't work. I'm saying that simulating doesn't always work. The first time I tried simulating a circuit that I had built and it worked, I had to build it one semiconductor at a time on the computer or the Simm just couldn't figure out what the output was. Oh yeah, it was a DC coupled jfet amplifier with automatic Idss compensation (so any jfet of that part number would work without adjusting for Idss).

Edit: I still think that Vgs is absurd. I don't know why that transistor would pass more than a couple of nanoamps with that bias. I'm saying your simulation program is wrong.

 

Hi-Z, I just read your post.

With the 1 FET design, an Ids of about 10-12 mA seemed to work well, so I try to get that now but I can't always do it when I'm trying to aim for a certain voltage or resistance somewhere in the circuit.

My original circuit was a Wheatstone bridge with the one FET as the variable resistance. I think my last version of the circuit consisted of two 660 ohm resistors "on top" and a 2.2K resistor opposite the FET with a 5K pot for balancing. The FET was right at the antenna and the rest was indoors, at the end of 50' of shielded, twisted wire cable. I moved the FET indoors and added the second to reduce sensitivity to temperature changes, but even when I try to replicate the original circuit, my sensitivity is like 1% of what it used to be. I figured it was due to the 50' of cable being between the FET and antenna instead of just supplying power to the FET. Needless to say, I was surprised when I moved both FETs out to the antenna, the sensitivity didn't return.

I used to have back to back zener diodes on the input to protect the antenna FET, but even the capacitance inherent in a diode makes the sensitivity worse. I've tried other things also and I still get the best sensitivity with no diodes. Putting very large capacitors across the bridge output can dampen some noise, but 4 volt lightning spikes appear totally unaffected. In any case, the in-amp does not like large caps across its inputs.

I've tried vaious low pass filters (<really> low pass) with no effect also and tried filters upstream, midstream and downstream with little variation. A lot of noise came from the 10M (low noise) resistors I used to have on the antenna to bleed excess charge, but as I've said, my signal is so small that even 10M bleeds a lot to ground. Going to higher resistance makes much more noise. I recently read something about the thermal noise produced by resistors and I was surprised at how easily it could get up to significant fractions of a volt when large resistances are used on an input. It must have been from something like that since nothing filtered it out.

 

#12,

I don't have any fancy-schmancy sim program. I found a website that has demonstration circuits to explain how they work and it lets one draw their own circuit while it does all the calcs. I just blank out their circuit and draw my own.
See: http://www.falstad.com/circuit/e-index.html

 

You have an intriguing story there, Darkstar! I can see I'll have to put my thinking cap on, but one thing that strikes me is that Zener diodes are notoriously capacitive. What I actually had in mind were small-signal diodes, which would limit your differential input voltage to about 0.6V. Is this enough to cope with the everyday signal (as opposed to lightning activity)?

 

Z,

I think a single small signal diode could work. I tried several once, but not just one. It's a lot easier to work on the indoor part of the circuit than the outdoor part, so, the easiest thing to do for now would be to insert one in the indoor part of the circuit and look for any changes. I'll try that once I reset my variables to get a signal big enough to show variations.

It seems like it would be easier to tune this circuit if I had some way to apply a signal of known size then I could make adjustments as needed to give me a strong output signal. Even so, I really need a starting point, such as for Rc, so I could adjust Rd1 and Rd2. With multiple pots to adjust it's impossible.

 

I think it's probably better to avoid using the simulation as a guide - don't forget, even if the fet model is OK, it would reflect only a single sample in terms of gate-source voltage characteristics.

I don't think you really need to worry too much anyway, because with split supplies there's quite a bit of latitude. So, you could assume a Vgs of, say, -2V at you chosen current, in which case the voltage across Rc would be 17V. This knowledge will enable you to set a tail current, which hopefully will be shared pretty much equally by the two fets (especially if they're a matched pair). I'm not sure what the "sweet spot" current is for the mpf102, but you could aim for 1mA (i.e. 2mA tail current).

Now you can choose the Rd values: the idea, for max headroom, is to end up with a Vd midway between Vs and positive supply. This actually defines the gain. You can have a larger gain by making the resistors larger in value than I've prescribed, but at the expense of headroom, and I think headroom will be important when you have large transients to cope with. I do think a pair of diodes across the inputs, plus a large C across the outputs ought to go a long way in reducing the effects of electrical storms.

Do note, though, that large common-mode movements in input voltage will cause the tail current to vary, and this will cause common-mode fluctuations in output voltage (avoided if you were to replace Rc with a current sink).

I don't think there's too much mileage in tweaking the current in order to maximise gain, but you could try if you really want to.

Now, having come up with a set of resistor values, you'll want to check the amplifier for gain. I think you could achieve this just by inputting small dc voltages - it should be pretty straightforward.

One more thing - make sure your fets are decent working transistors. Exposing jfets to thunderstorms isn't my idea of cossetting them, so your existing devices may not be working perfectly (or at all!).

 

Thanks for the tips, Z.
I used the sim program to see if I could come up with the combination of variables you suggested. You mentioned a Vgs of -2V at my chosen current. I've seen accounts of people using 5mA in FET audio amps so I figured that was a good target. I got the following stats in the sim:
+/-15V
Rd=2.43K Ω
Rc=1.29K Ω
zero pot=1K Ω
Vd=2.07V
Vs=1.39V
Ids= -5.33mA <
Vgs= -2.07V <
Vds= -680mV
linear region operation
gm=650uA/V

Next, I tried to adjust for Rd to be midway between Vs and the pos supply. This sim always shows Vgs being equal to Vd, so I no
longer had -2V for Vgs when Vd was where I wanted it. Anyway, I ended up with these stats:
+/-15V
Rd=4.7k Ω
Rc=7.62k Ω
zero pot=1k Ω
Vd=8.57 V <
Vs=6.52 V
Ids= -1.37 mA
Vgs=-8.57 V <
Vds= -2.05 V
saturated region operation
gm=1.85mA/V

Which of these sets of variables looks good to you?

Could you please define your term "tail current", I'm not sure I know what this is.

I have had one FET outside for over a year (shielded from the elements of course) and it still works. A couple others developed intermittant shorts from unknown causes, but I haven't been seeing the output patterns they gave. They tested good but failed in the circuit. While it would be a good idea to check my FETs, I feel relatively confident they are working.

With your favorite choice of variables from above, or some new ones, I'll try them out. It takes as much as a full day to gather data for each test unless it becomes obvious something is wrong. Then I can report the results.

At the moment, I'm running a test that is not completely stable, but so far appears to have very good signal strength. I used the tips I got here as guides and relied on some guesswork and gut feelings and compromised with the following variables. Some are not where I would normally set them, but I figured I'd try anyway.
+/-15V
Rd=743 Ω
Rc=1090 Ω
zero pot=1k Ω
Vd=9.57 V <
Vs=4.58 V
Ids= -7.31 mA
Vgs=-9.57 V <
Vds= -4.99 V
saturated region operation
gm=4.27mA/V

I'll have results tomorrow.

 

Well, the test I was running did not turn out well. The output just kept climbing. It had one 4V positive spike and one 3.5V negative spike.

I'm starting a run with the first list of variables listed above.