Hi, I've been working on a hardware RNG based on gating the time period of a mains cycle (from a small 12v transformer) against a PIC timer running at 5MHz.
Currently it's going pretty good but I'd appreciate some feedback before finishing up the project.
Concept;
I knew from previous projects measuring the stability and average freq of the AC mains that each mains cycle (and half-cycle) had quite a few uS of error, due to the chaotic nature of the AC mains system and everything in the world connected to it.
I wanted a hardware based RNG that produces really good quality entropy, and wasn't happy with most of the typical solutions like diode junction noise etc, which are prone to a problem called "break" and produce a substandard entropy but you don't really know.
This concept was to capture the least significant bit of a free running 5MHz counter, for every mains half cycle (each 10mS as my mains is 50Hz). This is pretty much immune to "break" problems, and on any failure of the mains the RNG will simply stop.
Procedure;
The PIC 16F628A runs from regulated 5v, xtal of 20MHz, and its timer1 runs as a free running counter at 5MHz. 12v AC is taken from a plugpack, and rectified and set by a pot to be a 0v-5v waveform. That waveform is gated by the PIC comparator set to 1v setpoint, and debounced in software to give one gate per 10mS.
Every gate incident causes the PIC CCP1 module to capture the free running timer1, and only the least significant bit is used, these bits are compiled into bytes and sent out the serial port to a PC for logging. The RNG makes exactly 100 bits per second (12.5 bytes/sec).
Currently it's going pretty good but I'd appreciate some feedback before finishing up the project.
Concept;
I knew from previous projects measuring the stability and average freq of the AC mains that each mains cycle (and half-cycle) had quite a few uS of error, due to the chaotic nature of the AC mains system and everything in the world connected to it.
I wanted a hardware based RNG that produces really good quality entropy, and wasn't happy with most of the typical solutions like diode junction noise etc, which are prone to a problem called "break" and produce a substandard entropy but you don't really know.
This concept was to capture the least significant bit of a free running 5MHz counter, for every mains half cycle (each 10mS as my mains is 50Hz). This is pretty much immune to "break" problems, and on any failure of the mains the RNG will simply stop.
Procedure;
The PIC 16F628A runs from regulated 5v, xtal of 20MHz, and its timer1 runs as a free running counter at 5MHz. 12v AC is taken from a plugpack, and rectified and set by a pot to be a 0v-5v waveform. That waveform is gated by the PIC comparator set to 1v setpoint, and debounced in software to give one gate per 10mS.
Every gate incident causes the PIC CCP1 module to capture the free running timer1, and only the least significant bit is used, these bits are compiled into bytes and sent out the serial port to a PC for logging. The RNG makes exactly 100 bits per second (12.5 bytes/sec).
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