please help!! 4 bit shift register design

Discussion in 'Homework Help' started by bluepit, Apr 2, 2007.

  1. bluepit

    Thread Starter New Member

    Apr 2, 2007
    im taking an introductory course in VHDL and im supposed to desgin a 4 bit shift register.

    the specifications are the following ::

    4-bit Shift Register
    The 4-bit shift register should be capable of doing all the following
    functions. Implement these functions using a Finite State Machine
    • SISO (Serial In Serial Out)
    • SIPO (serial In Parallel out)
    • PISO (Parallel in Serial out)
    • PIPO (parallel In Parallel Out)
    • COUNT UP (count from “0000” to “1111” and then roll over to “0000”)
    • COUNT DOWN (count from “1111” to “0000” and then roll over to
    • PROGRAMMABLE COUNT UP (Provide a start and an end value. The
    counter should check if the start is less than the end value and only if
    so should start counting from the start value and stop at the end
    value. The counter should be started only with a new start and end


  2. hgmjr

    Retired Moderator

    Jan 28, 2005
    A quick google session and I was able to locate this VHDL Programming Tutorial link.

    There are several other hits that might prove useful.

  3. Papabravo


    Feb 24, 2006
    I can do better.
    All the finite state machines you will ever see besides all the ones that you won't have certain things in common.

    They all have a set of inputs
    They all have a set of states
    They may or may not have a separate set of outputs.

    There is a Moore machine and a Mealy machine. The difference has to do with the presence of outputs.

    At each clock edge the machine uses the present inputs and the present state to compute the next state. A Mealy machine will also compute the new output fuction.

    Since you need a four bit register that pretty much tells you that you have sixteen states represented by four bits. NOw it is just a matter of constructing the boolean expression that determines the next value of each state bit from:

    The present inputs and the present state.
  4. Dave

    Retired Moderator

    Nov 17, 2003
    By strict definition, in a Mealy finite state machine the outputs are a function of the current state and the inputs, whereas in a Moore finite state machine the outputs are a function of only the current state.

    To the OP: have you derived a state diagram of your FSM? The first thing you need to do is ascertain your logical flow of operations, the first being a selection of operation as per your first post, and then sub-flows dependant on the selected operation. Then you need to draw a state transition diagram which will identify intermediate variables - these are things you should have done as part of your course thus far. Feel free to post up you state diagram from which point we can advise on programming.