# Please explain the relation of slew rate and EMI

Discussion in 'General Electronics Chat' started by jmbdr03, Mar 2, 2012.

1. ### jmbdr03 Thread Starter New Member

Feb 22, 2012
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Hi all,

i have read a lot of articles that slew rate control can reduce EMI, but haven't seen any explanation about how it can reduce EMI. Thanks!

2. ### jmbdr03 Thread Starter New Member

Feb 22, 2012
7
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reviewed my post and noticed that it has no questions, so please explain the relationship of slew rate and EMI, and if possible give references so i can read further. Thanks again.

3. ### studiot AAC Fanatic!

Nov 9, 2007
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Hello jmbdr03 and welcome to All About Circuits.

I take it from your question you know what slew rate is?

Slew rate is about the response to fast waveforms. The greater the slew rate the faster the rate of change of voltage (or current) that can occur.

Another way of looking at this is to observe that the faster the voltage can change the higher the frequency that can pass or be generated.

It is the 'or be generated bit' that is important because this is what leads to EMI.

go well

4. ### MrChips Moderator

Oct 2, 2009
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A pure sine wave signal has only one frequency.

A square wave has many frequency components, all the way to infinity, with decreasing amplitudes. Hence it this the square way itself that is generating the EMI at higher frequencies.

To reduce EMI we would want to filter out the unwanted frequencies. Taken to the limit, if we can reshape the square wave to look more like a sine wave, we would accomplish our goal.

The purpose of limiting the slew rate is to do exactly that, that is, to slow down the rising and falling edge of the square wave in order to remove the unwanted high frequencies which contribute to EMI.

5. ### crutschow Expert

Mar 14, 2008
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The slew rate (rise time) of a signal determines it's high frequency harmonics. The faster the rise time, the higher the harmonic frequencies. The relationship between rise time and the highest harmonic frequency generated is approximately f = .35 / Risetime. And of course the higher amplitude of the pulse, the higher the energy in the harmonics.

Thus reducing the slew rate or rise time reduces the frequency and amplitude of the harmonics generated. For that reason you don't want the slew rate to be any faster than needed for proper circuit operation.

6. ### studiot AAC Fanatic!

Nov 9, 2007
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Please note the slew rate, which is measured in Volts / second (or microsecond) is not the same as the rise time, which is measured in seconds (or microseconds)

7. ### steveb Senior Member

Jul 3, 2008
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Excellent point!

Slew rate limiting is a nonlinear operation. This makes it a little more complicated than just rise time (AKA bandwidth) limiting. While the above descriptions about bandwidth limiting are basicallly correct and along the right lines, a slew rate limit is amplitude dependent. Basically, high frequencies of very small amplitude would be allowed by a slew rate limit, but they are not as problematic to EMI since the amplitude is small.

In many practical cases, it might be a subtle point, but the given question is specifically about the relation of slew rate and EMI, and it seems that a discussion about amplitude (as mentioned by crutschow) is just as important as one about frequency to get the complete answer.

8. ### bountyhunter Well-Known Member

Sep 7, 2009
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A good thin to remember is that ANY waveform can be expressed as a series of sine waves (Fourier series) and the faster the waveform rises, the higher the frequency content. A vertical edge has theoretically energy out to infinity. The higher the frequency content, the more easily EMI radiates. The down side is that slowing the rising or falling edges increases switching losses.

9. ### crutschow Expert

Mar 14, 2008
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They may be measured by different parameters but they are two sides of the same coin. Of course rise time does not have an amplitude component and slew rate does.

10. ### crutschow Expert

Mar 14, 2008
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It only increase losses for power switches such as used in switching power supplies. For digital logic type switches, where the primary loss is the charging and discharging of the stray capacitances, the rise or fall time has little effect on power loss.

11. ### bountyhunter Well-Known Member

Sep 7, 2009
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True, I spent so many years designing power converters that I forget about low power junk. A guy I worked with interviewed a lady who had spent years working for the power company (dealing with HV transformers) and he asked her an interview question:

"So, we have a circuit using 5V logic..."

HER: "5V? Nothing will run on that...."