Hello i am trying to capture the first bit of an uart message with the CCP in capture mode, the problem is that once in a wile the interupt fires without any signal on the line, exactly when the interrupt is enabled(happens one every minute or so), i found this using an oscilloscope on the DEV2_LED, the delay between each uart frame is 20 ms, and the length of the frame is 2-3ms, i switch the interrupt off each time i receive the falling edge of the first bit of the frame and i putt it on back ~12ms after that, or at least that is what i want to do.
the ccp interrupt are enabled in high priority isr and thy are checked in low priority
a picture with the osciloscope can be see here , blue line DEV1_LED, yellow line UART,

void ActivateCcpInterrupt(u8 channel)
{
    switch(channel)
    {
        case 5:
            CCP5IF = FALSE;
            CCP5IE = TRUE;
            break;
        case 4:
            CCP4IF = FALSE;
            CCP4IE = TRUE;
            break;
        case 3:
            CCP3IF = FALSE;
            CCP3IE = TRUE;
            break;
    }
}

                //this part is inside a timer interrupt that fires every ms
                // the problem appears here afer the interrupt is se to enable the isr for the interrupt is executed without any signal on the uart, both of the lines are observed on the oscilloscope 
                //enabling the ccp interrupt after a 12ms delay
                if(ccp3IsDisabled)
                {
                    if(ccp3Timer-- == 0)
                    {
                        ccp3Timer = 12;
                        ccp3IsDisabled = FALSE;
                        ActivateCcpInterrupt(3);
                    }
                }
                if(ccp4IsDisabled)
                {
                    if(ccp4Timer-- == 0)
                    {
                        ccp4Timer = 12;
                        ccp4IsDisabled = FALSE;
                        ActivateCcpInterrupt(4);
                    }
                }
                if(ccp5IsDisabled)
                {
                    if(ccp5Timer-- == 0)
                    {
                        ccp5Timer = 12;
                        ccp5IsDisabled = FALSE;
                        ActivateCcpInterrupt(5);
                    }
                }

// this part is inside the low priority isr
 if(CCP3IF && CCP3IE)
    { //!< A capture interrupt is set for CCP3
        temp=CCPR3;
        CCP3IF=FALSE; //!< Set capture interrupt flag false
        CCP3IE=FALSE;  //!< Disable Capture interrupt
        DEV3_LED = !DEV3_LED;
        ccp3IsDisabled = TRUE;
        CCP_time_log(2,temp);    //!< Logging tmr value, for ccp3
    }

    if(CCP4IF && CCP4IE)
    { //!< A capture interrupt is set for CCP4
        temp=CCPR4;
        CCP4IF=FALSE; //!< Set capture interrupt flag false
        CCP4IE=FALSE;  //!< Disable Capture interrupt
//        DEV2_LED = !DEV2_LED;
        ccp4IsDisabled = TRUE;
          CCP_time_log(1,temp);    //!< Logging tmr value, for ccp4
    }

    if(CCP5IF && CCP5IE)
    { //!< A capture interrupt is set for CCP5
        temp=CCPR5;
//        COMPENSATE_TMR3(temp);
        CCP5IF=FALSE; //!< Set capture interrupt flag false
        CCP5IE=FALSE;  //!< Disable Capture interrupt
        DEV1_LED = !DEV1_LED;
        ccp5IsDisabled = TRUE;
         CCP_time_log(2,temp);    //!< Logging tmr value, for ccp5
    }

 

later edit: after a little bit of digging up the the isr doesn't execut exactly after the delay, it waits 5-7ms and after that the interrupt is triggered, what could cause this scenario?

 

I wonder what the manual says...

16.2.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in operating mode.

Otherwise I can't make any sense out of the code fragments you posted. It's always best to cut the code down to the simplest piece that demonstrates the problem. And all the module set-up code should be provided.