Broadly speaking, I'd like to know what's happening on each Q of a microcontroller's clock cycle.
What I do know is that the oscillator frequency used is divided by the MCU circuitry to make 4 oscillator pulses equal 1 instruction cycle. I know that each instruction is fetched, decoded, and executed, and that one instruction cycle is used to fetch, and a second to execute. What I don't know is, are separate things happening in each Q that make it so this setup is required?
I'm probably phrasing my question horribly. Is Q1 used to fetch the instruction's program memory address and load it into the program counter, then Q2 does what? Q3 and Q4?
What I do know is that the oscillator frequency used is divided by the MCU circuitry to make 4 oscillator pulses equal 1 instruction cycle. I know that each instruction is fetched, decoded, and executed, and that one instruction cycle is used to fetch, and a second to execute. What I don't know is, are separate things happening in each Q that make it so this setup is required?
I'm probably phrasing my question horribly. Is Q1 used to fetch the instruction's program memory address and load it into the program counter, then Q2 does what? Q3 and Q4?