I am going through lab 17 in the "Student Manual for The Art of Electronics," and I'm having some trouble understanding how phase detectors work. First of all, at the bottom of p. 416 (scan attached), it talks about how a simple XOR gate can be "fooled." It shows the filtered versions of the output signal as being flat in two different cases--but it seems to me that there's no way the filtered output signals would be flat, even if they were significantly filtered. For example, in the "TRUE LOCK" case, the peaks in the ref+sig output should result in bumps in the filtered output, followed by exponential decay. Am I missing something here?
Then, on p. 417 it talks about the CMOS 4046 and how it can't be "fooled." It shows a diagram in which the VCO input has a frequency two or three times greater than the reference input, and how the phase detector output has a frequency that is the same as the reference input. I am having a hard time understanding how this could be, simply from the standpoint of how CMOS gates work. I've attached my understanding of what I expect the phase detector output should look like. Obviously my understanding is wrong, but I don't know why, so I'd appreciate any explanation. Thanks.
Then, on p. 417 it talks about the CMOS 4046 and how it can't be "fooled." It shows a diagram in which the VCO input has a frequency two or three times greater than the reference input, and how the phase detector output has a frequency that is the same as the reference input. I am having a hard time understanding how this could be, simply from the standpoint of how CMOS gates work. I've attached my understanding of what I expect the phase detector output should look like. Obviously my understanding is wrong, but I don't know why, so I'd appreciate any explanation. Thanks.
