PCB ground return current, transmission line question

Thread Starter


Joined Sep 18, 2010

I am currently working on a few projects with PCB boards and I had a few questions about them. One system contains a 24 bit ADC so I’m trying to think of everything to reduce noise and other problems. Right now my questions are just about ground return currents and transmission line models. So here are the questions.

I’m trying to figure out if I understand ground current return loops so here are some examples and please tell me if or how I got any loops wrong.

From figure 1 when the signals are high (there are two separate PCBs, internally all the gnds are connected as well as all the Vccs through solid planes on both boards. All the signals are digital at about 1MHz, 1-6ns rise time):
Sig1: Vcc2;sig1;gnd1;gnd;Vcc;Vcc2.
Sig2: Vcc1;sig2;gnd2;gnd;Vcc;Vcc1.
IC1 Internal current use: Vcc1;IC1;gnd1;gnd;Vcc;Vcc1.
Sig3: Vcc2;sig3;gnd3;gnd;gnd;Vcc;Vcc2

For signal 3, would the proper technique be to send a gnd cable along with the signal and would this gnd cable be connected at gnd2 or gnd, does it make a difference? Where would I connect it on PCB 2, at gnd3? Would the gnd cable not introduce noise back to the ADC board, or because of the solid ground on PCB2 only ground return for signal 3 would flow in that cable and everything else would flow through its own gnd?

I’m planning on routing (output) signals going to other boards such as sig3 through a logic buffer that will sit right at the board’s edge. Would this help reduce noise from other boards or is there some other recommended method? Am I missing some other consideration?

To model as a transmission line; knowing that the rise time of the buffer in a 74HC package is 6ns, and using this calculator http://www.pcb123.com/help/calculators/microstrip.html to find the propagation speed in my PCB track as 0.1431 ns/in à 6.99in/ns*6ns = 41.93in/2 (div by 2 b/c of return track)= 20.96in. Alternatively, the maximum clock speed of components on PCB1 is 20MHz, then wavelength/10 = c/(f*sqrt(er)) = (299792458/(sqrt(4.5)*20000000))/10 meters = 27.81 in.
Then if the total wire and PCB track carrying sig3 is less than 20” I don’t have to worry about the tracks/wire/connection not matching impedance to each other, right?

Also, for on board traces, assuming a min rise time of 1 ns (it’s not given from some ICs) then if the length of the trace is less than 6.99/2=3.5” then I also don’t have to worry about impedance and such, right?

Another question; say I have a three layer board with 2 solid ground planes below a signal plane. Say a signal originating from Ica and going to ICb is routed on the top signal layer. Now the question is if the ground return current flowing below the signal flows on the top or bottom ground plane. I think the answer is; it depends to which plane the ground of ICb is connected to, if that ground is connected to the top layer it will flow in the top otherwise it will flow in the bottom. Is that correct?

Finally, would it be okay if I post my ADC system PCB footprints to see if anyone has comments, in a new thread?

Thanks in advance,



Joined Feb 5, 2010
Convention usually requires analog, or high current elements have seperate ground return pathways from digital components, that connect at ONE point only, to deal with the issues you refer to.

You are on the right path by considering ground plane current flows, but the emphasis should be placed on power pathways and signal pathways and strive to prevent close interaction between the two.(identical requirements exist for the opposite pole of the power supply)

As for signal pathways the only true need is to keep the signals close enough together in a temporal sense, by using traces that are of similar length. And this only becomes a major issue with large circuits that operate at very high speeds.

Thread Starter


Joined Sep 18, 2010
Convention usually requires analog, or high current elements have seperate ground return pathways from digital components, that connect at ONE point only, to deal with the issues you refer to.

You are on the right path by considering ground plane current flows, but the emphasis should be placed on power pathways and signal pathways and strive to prevent close interaction between the two.(identical requirements exist for the opposite pole of the power supply)
Thanks for the reply. I'm trying to do that, however, the ADC data sheets and manufacturer (AD) say to connect the analog and digital grounds pins of the ADC near the ADC (sigma delta type) and connect both to analog ground, and that there should probably be only one ground anyway. Because of this I'm trying to figure out if I should have separate digital/analog grounds.

I have a four layer PCB; top and bottom are signals, there is a ground plane and I'm debating if the forth layer should be power or another ground, i.e. two center ground planes. If I have two ground planes then the power will be spliced on the bottom layer between signals.

Actually, If I have a power layer I don't see how I can give a separate ground pathways for power and signal since the power can take any pathway on the board. Unless there is some rule as to where the power pathway is, even if it can flow on a full plane.

Now if analog and digital grounds are connected at the ADC to analog ground I'm trying to figure out on which side of the board to route each signal so that it can closest to the ground plane in which its return current is flowing. Is that actually important?

The other issue I'm having is trying to figure out what needs to be separated from what. I.e. I know that the logic signals should be separate from my analog input signal to ADC. However, what about the 5v power input, the 2.5v reference to the ADC and a transistor controlling a LED? Are the last two considered signals and should they be kept separate from each other and from the above signals? So when you say to keep signals away from power what what is considered a signal?

You see, at the ADC I have four signals; digital (crossing over from the digital half of the board), analog, power and voltage reference, which is why I'm trying to figure out the optimum way of doing this. So in the digital half of the board, except controlling the power ground return issue, it's pretty simple, but it gets confusing for me at the ADC.



Joined Feb 19, 2009
4 layer board, signal on top and bottom, one inner board is power, one is ground.

Do not use 2 inner ground planes, it will be messy. Spread bypass caps liberally across surface of board between Vdd and Vss (power/ground), anyplace you have room, add a 0.1uF cap between the two inner layers, as well as from IC Vcc/Vdd to Ground. Add larger caps, 10-22uF, low ESR less liberally than the 0.1uF on the board, mostly around IC power inputs.

If the analog load is high, use a completely isolated supply and optocouplers for communications. If the load is simply a flash ADC to a processor, you don't need that level of isolation, only solid/stable power and ground planes with a good power supply.

Trying for a 5 layer board to keep power in the middle has been done, but doesn't provide advantages. Doubling the layers, literally, is done, but power and ground planes are usually matched for surface area, extra V+, add ground. If you are working in the Ghz Range, then routing gets very tricky, as the slightest parasitic capacitance or inductance will cause bad behavior. Computer motherboards keep the signal lines running under 1Ghz if possible, the higher frequencies are only "on die" in the CPU. Use any "unused" signal area as more paths to ground as well.

--ETA: There are entire books and semester long college courses on high speed mixed signal PCB design, I'd steer you toward a library, honestly. Contacting the component house can also get you some good advice.
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Thread Starter


Joined Sep 18, 2010
So I finished designing the PCB board for this project and I wanted to see if there are any comments on it. I also have a few very specific questions.

First, the board is centered around a FT232 USB to serial device, of which I'm using bit bang mode. This device is connected to a micro which is in turn connected to an ADC. Some pins of the device also connect to another board through a buffer. The placment on the board from left to right is ADC-Buffer-micro-FT232.

I took the suggestions so there are four layers, signal-gnd-power-signal. I also sprinkled a few extra 0.1uF caps on the board. I'm attaching images of the silk, top, power, bottom layers as well as some close ups of the ADC and FT232 areas. The ground plane is continues with no separations so I did not include an image.

The questions are as follows:
1. Are there any comments on the cap distribution, should I add more? I tried to follow the manufacturers recommendation where possible, but otherwise I placed 10 followed by 0.1uF next to each IC. What problem could arise from too much capacitance between power/gnd?

Although FTDI did not show caps on the the USB +/- data lines. I saw a prototype board from them that included 47pF for each USB data line. I included these as well but I wasn't sure if I should have.

2. In ExpressPCB, is the difference between a Via and Pad only in that the pad gets a solder mask?

3. As you might have noticed, my top layer has a lot of empty room and my bottom signal layer is almost empty. Should I pour ground in the empty locations? If so, should I connect the pour to the gnd plane at more than one location and where should I do that. Any comments on the ground pour I have around the crystals?

4. I use a buffer with 8 lines. However, I only use 7 lines. Should I connect the 8th line input to power or gnd directly?

5. Finally, as you can see, there are some lines from the FT232 that connect to a buffer and then go to another board. Considering that this second board drives valves, should I worry about noise coming back to the current board? If so what else can I do other then using this buffer?

In addition, you'll notice that one line leaving the board to the other board is a ground connection which will connect the grounds of the two boards. The reason for this is to provide a easy return current path for the signals between the boards. I'm worried that this will introduce noise between the boards. Is there anything I should know/consider here?
You'll notice that the power connector is very close to that buffer so if any current does come back it will flow immediately to the power connector and not spread in the board, hopefully.

When determining the maximum length of the wire carrying the logic signals between boards, other than using my calculation in my first post, what should I be aware of when specifying the maximum length of this wire?

Finally, seeing as this is my first with SMD of the 0603 type, I'm wondering if there are any comments on my placement of them on the board.

Thanks in advance for any info,