I am working through Lab 13 of "Student Manual for the Art of Electronics," and I have a few basic questions on section 13-4 (see attachment). First, I am instructed to drive the circuit "with a TTL level from the breadboard oscillator, pulled up to +5V, through a 1k resistor." First of all, I assume they mean I am supposed to pull up the oscillatory TTL signal so that it has a 5V dc offset, right? And second, how exactly am I supposed to accomplish this using a 1k resistor?

I went ahead and performed the experiment without doing an pull-up to the input, and I still see the effect I think they're getting at: the output is no longer a perfect square wave, but is rounded, showing capacitive effects. Is this because the MOSFET acts like a resistor in parallel with a capacitor, and at higher input frequencies the capacitor can't charge fast enough to keep up? Thanks for the help.

 

The instructions aren't completely clear, but then I don't know what the breadboarded oscillator circuit they are talking about looks like. My guess is that when they talk about being pulled up to 5V through a 1kΩ resistor, they are talking about the output pullup resistor -- the one in the figure just above it that is 10kΩ in the diagram.

What you should see as you increase the frequency is that the waveform gets distorted due to the RC time constant of the pullup resistor and the MOSFET capacitance, much as you described. Of course, the distortion is there at low frequency, as well, but the time that it takes to get through the distortion is small compared to the total period. At a sufficiently high frequency, it just isn't able to get through the distortion before the period ends.

You should also see that the waveform is not symmetric - the LO-HI output transition is probably affected significantly more than the HI-LO transition.

 

WBahn, back in chapter 10 of the student manual they talk about RC oscillator (using a 311, open collector comparator). the 555 relaxation Oscillator, the 555 sawtooth oscillator, and the Wien Bridge oscillator using a 411.

Earlier in this chapter (13) the authors stated

All respectable gates use active pullup on their outputs, to provide firm Highs as well as lows.

You will confirm in the lab that the passive pullup version not only wastes power but also is slow.

My guess would be they certainly would use the 555 astable oscillator.

 

Which makes me more certain that the pullup they are talking about has nothing to do with the oscillator, but rather the pullup resistor in the diagram shown.

 

My original read was it referred to a pullup resistor, with the lab designed to illustrate the differences between active pullups and resistive pullups. Since I own the same student manual, I was afforded the opportunty to confirm.

 

Thanks for the responses, and sorry I haven't responded sooner. I spent the last few weeks preparing for my PhD defense (not in electrical engineering, obviously ). What you say about the MOSFET introducing capacitive effects makes sense. However, I am still puzzled by one aspect of my results. As you can see in the waveforms I sketched in the attached pdf, the output waveform is inverted from the input, but not in the way I would expect. Since the input switches between 0v and 5v, I would expect the output to do the same. However, the low state of the output is -2v. Also, for the output the decay to the low state is much more rapid than the rise to the high state. I'm not sure if this is to be expected from some characteristic of the MOSFET or what. Thanks in advance for the help.

 

Thanks for the responses, and sorry I haven't responded sooner. I spent the last few weeks preparing for my PhD defense (not in electrical engineering, obviously ). What you say about the MOSFET introducing capacitive effects makes sense. However, I am still puzzled by one aspect of my results. As you can see in the waveforms I sketched in the attached pdf, the output waveform is inverted from the input, but not in the way I would expect. Since the input switches between 0v and 5v, I would expect the output to do the same. However, the low state of the output is -2v. Also, for the output the decay to the low state is much more rapid than the rise to the high state. I'm not sure if this is to be expected from some characteristic of the MOSFET or what. Thanks in advance for the help.

Do you have the scope channel that is monitoring the MOSFET drain waveform AC-coupled (generally a front panel switch, or possibly a menu-selectable option)? That could account for your observed results.

 

You were absolutely right--switching to DC coupling fixed it! Thanks!

 

You were absolutely right--switching to DC coupling fixed it! Thanks!

Been there, done that.

 

Ron,

Who hasn't ....

 

Just wondering if anybody else is having trouble posting a new thread...I've been unable to do so for one week. Whenever I try, I get a "Server Error." So anyway, I hope you'll forgive me for starting a new--but related--topic on this thread. It has to do with active, rather than passive, pull-up in a MOSFET circuit.

On p. 317 of the Student Manual for The Art of Electronics (attached), I am instructed to construct a simple circuit in which a p-type MOSFET acts as a pull-up resistor. I have constructed this circuit and it works fine, but I am now trying to understand why it works as an inverter.

I understand why a high input results in a low output: with a +5v input, the p-type MOSFET assumes a very high input resistance, while the n-type MOSFET assumes a very low input resistance, so that a simple voltage divider calculation shows that the output should be very nearly zero.

However, I am having trouble understanding why the output should necessarily be high when the input is low. When the input is 0v, as far as I understand both the p-type and the n-type MOSFETs should have equal input resistances, which would result in the output being +2.5v. I understand how if the input were -5v, then the output would be +5v, because then the p-type would have low input resistance and the n-type would have high input resistance. But I don't get why an input of 0v results in an output of +5v. Thanks for the help.

 

When the input is 0V, the N-channel is off and the P-channel is on. When the input is 5V, the N-channel is on and the P-channel is off.

 

Yeah, that's how I thought I understood it because that's the only way the circuit analysis makes sense. However, p. 144 of "The Student Manual for the Art of Electronics" (attached) shows the I-V curves for PMOS and NMOS transistors, and both of them show zero conduction at V_{GS}=0. This would imply that an input of 0V would result in both NMOS and PMOS transistors acting as open switches, and the output would then be "float," not "high." Am I misunderstanding the attached plot?

 

Yeah, that's how I thought I understood it because that's the only way the circuit analysis makes sense. However, p. 144 of "The Student Manual for the Art of Electronics" (attached) shows the I-V curves for PMOS and NMOS transistors, and both of them show zero conduction at V_{GS}=0. This would imply that an input of 0V would result in both NMOS and PMOS transistors acting as open switches, and the output would then be "float," not "high." Am I misunderstanding the attached plot?

this depends on whether you are using enhancement mode or depletion mode MOSFETs

 

Yeah, that's how I thought I understood it because that's the only way the circuit analysis makes sense. However, p. 144 of "The Student Manual for the Art of Electronics" (attached) shows the I-V curves for PMOS and NMOS transistors, and both of them show zero conduction at V_{GS}=0. This would imply that an input of 0V would result in both NMOS and PMOS transistors acting as open switches, and the output would then be "float," not "high." Am I misunderstanding the attached plot?

V_{GS}=0 means Gate-to-source voltage=0, not gate voltage =0. If the source of a PMOS enhancement mode transistor is at 10V, then to turn it off, the gate needs to be at 10v. That's a gate-to-source voltage of 0v.

 

Got it. That makes perfect sense. When the input is 0V, then the output is 5V, which makes the gate-to-source voltage for the PMOS -5V, which clearly puts it in the conducting regime. Thanks so much.