Pass Transistor CMOS power dissipation

Thread Starter

elettro2021

Joined Feb 8, 2022
14
Hello,I have following circuit

2022-02-22_095416.png
and I need to prove that this circuit has non-zero static dissipation.
Assume the inverter switches ideally at VDD/2, neglect body effect, channel length modulation and all parasitic capacitance.

Now When A=B= VDD, the voltage at node x is VX=VDD-VtN,but how can I prove analytically that there is no static power dissipation for inverter cmos? Because P=(Vdd^2)/Rp how can I compute equivalente resistance Rp for PMOS M2?
 

Thread Starter

elettro2021

Joined Feb 8, 2022
14
excuse me.....text error Now When A=B= VDD, the voltage at node x is VX=VDD-VtN,but how can I prove analytically that there is no zero static power dissipation for inverter cmos?
 

Thread Starter

elettro2021

Joined Feb 8, 2022
14
M2 PMOS works in velocity saturation
Rp=Vds/Idp=Vdsat/(k'p*(w/l)*Vdsat*(2.5-2.07-0.4)) and I neglet Vdsat/2
w/l=6 k'p=30*10^-6 Vdsat=1 V
Rp=185kOhm

Is it correct my way of thinking??
Please help me.
 

DickCappels

Joined Aug 21, 2008
8,812
Let's call the threshold 0.4 V. The gates are There is 1.25V of forward bias between each transistor's gate and source, so there is conduction overlap during most of the transition on the input.

That's as far as I can go as I have not studied MOSFETs in depth. The fellow who was helping you is a moderator here and will in all likelihood be aware of where you are with your problem and back to help you.
 
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