Hello everyone,

I've got a board with several parallel buses running around, each operating at different speeds. Normally this isn't a problem for me as the boards are manually routed, but this time it's auto routed so I'm having to spec the matching within the buses.

Some of these receivers spec their skew they can accept, but others don't; hence my asking.

What do people use as a rule of thumb of length matching parallel bus? Some seem to just want 1/10 of a clock cycle(~100Mhz clk), while others want 1/100(200Mhz clk). What's the general rule you all follow? Or is there none?

 

the higher data rates you are using, the more imortant it is to keep them the same langth. also, it has been found that good rf stripline (transmission line) design is important at high data rates, corners and bends must be proper to prevent reflections from impedance bumps.