# P-MOSFET Problem to Solve

#### CrktMan

Joined Nov 29, 2005
34
Circuit is attached.
Determine the dc voltages, assuming K = 1 mA/V2 and VTH = 1V

Formulae for n-channel MOSFET

iDS = K[2(vGS-VTH)vDS - v^2DS] for triode region
iDS = K(vGS-VTH)^2 for saturation region

(I'm not sure why VTH is not given negative for this P-channel MOSFET - any suggestions?)

My solution (not sure!):

Let us consider P-channel MOSFET (as shown in picture) is operating in saturation.

IDS = K(vGS-VTH)^2 [ we have I = Is = Is = IDS = 2mA]
or, 2 = 1 (VGS - 1)^2
or, VGS = 1 plus/minus 2 square-root
or, VGS = 2.141V or -0.414V

As for P channel, VGS has to be less or more negative than that of VTH.
So, VGS = -0.414V

Applying KVL from Source to Get:

10 - VS - VSG = 0
or, VS = 10 + VGS = 9.59V

Now, VD = 6.8*2 - 10 = 3.6 V

VDS = VD - VS = 3.6 - 9.59 = - 5.99V

So, VGS = VG - VS
or, VG = -0.414 - 9.59 = 9.18V

Test, for saturation VDS ≤ VGS - VTH
-5.99 ≤ -0.414 - 1 true!

cktMan

#### n9352527

Joined Oct 14, 2005
1,198
Could you clarify which voltage(s) to calculate? And is the 13.6V at the bottom of the R specified or did you come up with it through calculation?

#### CrktMan

Joined Nov 29, 2005
34
Originally posted by n9352527@Apr 3 2006, 07:07 PM
Could you clarify which voltage(s) to calculate? And is the 13.6V at the bottom of the R specified or did you come up with it through calculation?
[post=15772]Quoted post[/post]​
Voltages to calculate are: VD, VG and VS, VGS

13.6 V just I calculated, not given.

#### n9352527

Joined Oct 14, 2005
1,198
1. Are you sure it is a PMOS? That is an NMOS symbol, but the biasing and current flow are typical of a PMOS.

2. VTH is usually negative for an enhancement-mode PMOS (which is the case for most devices out there), positive VTH for a PMOS indicates a depletion-mode device. Please check that it is not an error to specify a positive value and the device is indeed a depletion-mode PMOS.

3. Could you confirm that the bottom end of the resistor is connected to an unknown voltage instead of ground? That downward arrow is sometime used as analogue ground symbol. If it is grounded, then there would be no solution to the circuit.

4. You are missing something on the KVL from source to gate.

10 - VS - VSG = 0
or, VS = 10 + VGS = 9.59V

VS should be 0.414V above VG, _if_ the device is in saturation and VGS is -0.414 as you calculated above.

5. Where did you come up with VD = 6.8*2 - 10 = 3.6 V from? It looks like something is not right here.

6. I notice in your calculation you came up with:

So, VGS = VG - VS
or, VG = -0.414 - 9.59 = 9.18V

The circuit diagram shows that the gate is earthed (i.e. VG = 0V). VS + VGS should be zero.

#### CrktMan

Joined Nov 29, 2005
34
Originally posted by n9352527@Apr 4 2006, 08:31 AM
1. Are you sure it is a PMOS? That is an NMOS symbol, but the biasing and current flow are typical of a PMOS.

2. VTH is usually negative for an enhancement-mode PMOS (which is the case for most devices out there), positive VTH for a PMOS indicates a depletion-mode device. Please check that it is not an error to specify a positive value and the device is indeed a depletion-mode PMOS.

3. Could you confirm that the bottom end of the resistor is connected to an unknown voltage instead of ground? That downward arrow is sometime used as analogue ground symbol. If it is grounded, then there would be no solution to the circuit.

4. You are missing something on the KVL from source to gate.

10 - VS - VSG = 0
or, VS = 10 + VGS = 9.59V

VS should be 0.414V above VG, _if_ the device is in saturation and VGS is -0.414 as you calculated above.

5. Where did you come up with VD = 6.8*2 - 10 = 3.6 V from? It looks like something is not right here.

6. I notice in your calculation you came up with:

So, VGS = VG - VS
or, VG = -0.414 - 9.59 = 9.18V

The circuit diagram shows that the gate is earthed (i.e. VG = 0V). VS + VGS should be zero.
[post=15802]Quoted post[/post]​
Sorry That I took the bad scan, please take the 2nd pic that has -10V at the bottom of the Drain.

Now, I am sure it's a P-MOSFET, based on it's arrow indication.
You sound right that Gate is grounded.

#### n9352527

Joined Oct 14, 2005
1,198
oops!

#### n9352527

Joined Oct 14, 2005
1,198
This is one of the strangest exercise circuit I've ever came across, and the positive VTH doesn't exactly help either!

Assuming that all the parameters and circuit are correct, the first observation is that VD can be calculated directly from the voltage drop across the drain resistor:

VD = -10V + 2mA*6k8 = -10V + 13.6V
VD = 3.6V

Then from the value of VD we can see that the transistor is always in linear region, no matter what the value of VS is, because:

|VDS| < |VGS - VTH|, holds true for all possible value of VS.

VDS and VGS could be obtained from:

VDS = VD - VS
VDS = 3.6V - VS (1)

VGS = VG - VS
VGS = 0V - VS = -VS (2)

The drain current in the linear region is given as:

ID = K[2(VGS - VTH)VDS - VDS^2] (3)

Substituting (1) and (2) into (3) and filling the values of ID and VTH:

2 = 1[2(-VS - 1)(3.6 - VS) - (3.6 - VS)^2]

Which can be simplified to a quadratic equation of:

VS^2 + 2VS - 22.16 = 0

Solving for VS:

VS1 = -5.85V
VS2 = 3.82V

VS1 is not a possible solution since VS has to be higher than VD, therefore VS2 is the correct source voltage. Calculating the VGS and VDS:

VGS = 0 - 3.82V = -3.82V

VDS = 3.6V - 3.82V = -0.22V

#### CrktMan

Joined Nov 29, 2005
34
Originally posted by n9352527@Apr 5 2006, 11:02 AM
This is one of the strangest exercise circuit I've ever came across, and the positive VTH doesn't exactly help either!

Assuming that all the parameters and circuit are correct, the first observation is that VD can be calculated directly from the voltage drop across the drain resistor:

VD = -10V + 2mA*6k8 = -10V + 13.6V
VD = 3.6V

Then from the value of VD we can see that the transistor is always in linear region, no matter what the value of VS is, because:

|VDS| < |VGS - VTH|, holds true for all possible value of VS.

VDS and VGS could be obtained from:

VDS = VD - VS
VDS = 3.6V - VS (1)

VGS = VG - VS
VGS = 0V - VS = -VS (2)

The drain current in the linear region is given as:

ID = K[2(VGS - VTH)VDS - VDS^2] (3)

Substituting (1) and (2) into (3) and filling the values of ID and VTH:

2 = 1[2(-VS - 1)(3.6 - VS) - (3.6 - VS)^2]

Which can be simplified to a quadratic equation of:

VS^2 + 2VS - 22.16 = 0

Solving for VS:

VS1 = -5.85V
VS2 = 3.82V

VS1 is not a possible solution since VS has to be higher than VD, therefore VS2 is the correct source voltage. Calculating the VGS and VDS:

VGS = 0 - 3.82V = -3.82V

VDS = 3.6V - 3.82V = -0.22V
[post=15851]Quoted post[/post]​
I think you have come with right solution. Thank you>
"This is one of the strangest exercise circuit I've ever came across, and the positive VTH doesn't exactly help either!" - I totally agree with your opinion.

Comments: In order for to work in the Triode (Linear) region, the following condition has to be satisfied for a P-MOS transistor:
VDS VGS-VTH.
However, your solution holds true for considering VS = 3.82V.

Strange(!): your solution also holds true for considering VS = -5.82V.

This problem was given in a licensing test, I think, to test students' technical morals, not the practicality of circuit design!

#### n9352527

Joined Oct 14, 2005
1,198
Originally posted by CrktMan@Apr 6 2006, 06:31 AM
Strange(!): your solution also holds true for considering VS = -5.82V.
[post=15891]Quoted post[/post]​
Except that we know VS must be higher than VD = 3.6V, and that precludes VS = -5.82V. The way the circuit is set-up meant that the device is always operating in linear region.