It's been a while since I posted here, so hello again everyone

I've been messing some more with microcontrollers, and I'm in a situation where I'd like to switch power to a load connected to ground with the output of a uC. The microcontroller outputs are 3.3V and the supply voltage for the load is 48V. I've attached an image of what I'm thinking about, but it seems too simple to work. The FET is a P-Channel logic level MOSFET (should switch with -2.5V). In this case, would a logic high at the gate switch the 48V to the load?

Obviously, there might be better solutions. Any suggestions? I want to use this type of high side topology simply because I've never done it before, so moving the load and using an N-channel is out of the question Thanks in advance.

 

This MOSFET will be either ON or .... ON, depending on the PICs output.

EDIT: it will actually either be destroyed or destroyed, Vgs is being greatly exceeded.

Simply speaking, a PMOS FET is switched with the voltage difference between gate and source, as the n-channel FET. Only that here the source is at the 48V. So you need to bring up the voltage for the gate to:

48V to turn the MOSFET OFF
48V - max Vgs to turn it ON.

You need a level shifter.
First determine at what frequency you want to switch this thing and what will be the load.

We were just talking about this here: http://forum.allaboutcircuits.com/showthread.php?t=64575&page=2

 

Ah I see.

The switching frequency is extremely low. I'm not using PWM. At maximum, it would switch once a second or so. The load will most likely be inductive (yes, I realize I need a protection diode across the load ) drawing 500 mA max.

If I understand what you're saying, could I use a logic level N-Channel to switch 48V on and off to the gate of the P-Channel, thus turning it on and off? I've attached an image of what I'm thinking, I'm just not entirely sure about the selection of R1 and R2. They would have to be something that apply a voltage higher than the threshold, correct?

Thanks again.

 

yes. only that the n-channel FET is inverted, the source goes to Gnd.

When the NMOS FET is off the PMOS will have the gate tied to 48V,it will be off. When the NMOS is switched ON, the resistor divider will provide the voltage to the gate. Calculate them to have the nominal Vgs at the PMOS gate. For a standard FET that would be -15V (or 33V from PMOS gate to Gnd). This resistor divider method only works if the 48V is more or less constant. You can also put a zener diode between source and gate if it isn't.

The n-channel FET needs to be a logic level one with low Vgs threshold.

 

Whoops, I forgot about that. Here is a revised schematic with part numbers and the like. Think it'll work? My FETs may be oversized, but that's okay for now I suppose.

Thanks for the help

 

Looks like it should work. For slow switching it should be ok.

 

Looks like it should work. For slow switching it should be ok.

Any idea what my switching speed limits would be? If I wanted to take this and adapt it to a PWM circuit, how could I increase the switching frequency?

 

I've done a little research and it seems like the values of R1 and R2 would be the limiting factors on the switching frequency. Is this due to the FET's gate capacitance?

 

I've done a little research and it seems like the values of R1 and R2 would be the limiting factors on the switching frequency. Is this due to the FET's gate capacitance?

Yes, a few kΩ is way to much. To charge a gate rapidly you need to employ transistor driver stages, they connect the gate (via a low value gate resistor) to a low impedance source. This is the bypass capacitor which is connected to the power supply.

You find these transistor stages in dedicated gate drivers (example). You could possibly build one yourself too.

 

The 1k from the NMOS gate to ground just wastes power. A resistor there is needed to keep the transistors OFF if you expect to have +48V on when the uC is disconnected. In that case, a large value like 100k is sufficient.

 

Yes, a few kΩ is way to much. To charge a gate rapidly you need to employ transistor driver stages, they connect the gate (via a low value gate resistor) to a low impedance source. This is the bypass capacitor which is connected to the power supply.

You find these transistor stages in dedicated gate drivers (example). You could possibly build one yourself too.

If I were to reduce the values of R1 and R2 by a factor of 5 (so 1000Ω and ~460Ω, respectively), would that help at all? Is there a way to determine the upper limit of the switching frequency? For this project, I only need it to switch slowly, but I may eventually apply it to PWM at 1-2 kHz. Is this where I would need a gate driver?

 

If I were to reduce the values of R1 and R2 by a factor of 5 (so 1000Ω and ~460Ω, respectively), would that help at all? Is there a way to determine the upper limit of the switching frequency? For this project, I only need it to switch slowly, but I may eventually apply it to PWM at 1-2 kHz. Is this where I would need a gate driver?

When lowering the resistance you have to keep in mind the power dissipation for the n-FET and the Zener.

2kHz doesn't sound too much. You can calculate the gate charge time using the total gate charge parameter from the datasheet of the MOSFET and the driver impedance (the gate resistor has the biggest impact here).

Have a look at page 7:
http://www.microsemi.com/en/sites/default/files/micnotes/APT0103.pdf

 

Here's another related question:

If I changed the supply voltage to +12V, I would have to adjust R1 and R2 accordingly, correct? Here is my thinking. If the supply voltage is +12V and the Vgs max threshold of my P channel FET is -4V, I would want to provide at least +8V (from P-FET gate to ground). To be safe, would I want to go below the +8V, say +6V? Or would I want to go above the +8V, say +10 V?

By my logic, I'm thinking the voltage from gate to ground should be +6V. Then I would just make my resistor divider halve the supply voltage, correct? I've attached a new schematic...thanks for the help

 

Here's another related question:

If I changed the supply voltage to +12V, I would have to adjust R1 and R2 accordingly, correct? Here is my thinking. If the supply voltage is +12V and the Vgs max threshold of my P channel FET is -4V, I would want to provide at least +8V (from P-FET gate to ground). To be safe, would I want to go below the +8V, say +6V? Or would I want to go above the +8V, say +10 V?

By my logic, I'm thinking the voltage from gate to ground should be +6V. Then I would just make my resistor divider halve the supply voltage, correct? I've attached a new schematic...thanks for the help

Have a look at figure 3 of the datasheet. You need to provide at least -6V to be able to draw some Amps.

-4V is defined as maximum threshold at 250uA drain current.

So yes your -6V should be ok.

For future projects it helps you and others if you put equal power supply terminals all on the same side. Usually TOP is something positive, Ground or negative BOTTOM. Signal flow from left to right.

Of course this applies only where it's possible. But it greatly augments readability of your schematics, especially when they get bigger... and they will.

 

If your NFET is IRLR110 or IRLU110, it is only spec'ed down to Vgs=4V. I would use one spec'ed to 3.3V or below.
Your PFET is not spec'ed for Vgs less than 10V. It is good for 20V, so you only need one resistor for a 12V supply.

 

Oops, I didn't see the voltage has changed.. that was 48V before right?

Your PFET is not spec'ed for Vgs less than 10V.

What do you mean? There are several curves for Vgs less than 10V...

If your NFET is IRLR110 or IRLU110, it is only spec'ed down to Vgs=4V. I would use one spec'ed to 3.3V or below.

At 3V Vgs you can draw more than 1A, that should be much more than sufficient, shouldn't it?

 

Oops, I didn't see the voltage has changed.. that was 48V before right?



What do you mean? There are several curves for Vgs less than 10V...



At 3V Vgs you can draw more than 1A, that should be much more than sufficient, shouldn't it?

Figures 1, 2, and 3 are typical performance curves. Guaranteed performance is in the spec tables.
Attached clips are copied from the IRFR9110 datasheet. Note that Rds(on) is only specified at Vgs=-10V. If |Vgs| is below 10V, Rds(on) may be greater than 1.2Ω. I like to design to guaranteed specs (comes from working as a design engineer for 40 years).

 

Figures 1, 2, and 3 are typical performance curves. Guaranteed performance is in the spec tables.
Attached clips are copied from the IRFR9110 datasheet. Note that Rds(on) is only specified at Vgs=-10V. If |Vgs| is below 10V, Rds(on) may be greater than 1.2Ω. I like to design to guaranteed specs (comes from working as a design engineer for 40 years).

Ok, I have lived less years than you have worked as an engineer.

So , are you saying the typical transfer curves are not good for anything?

I would assume that, let's say if I wanted to draw 100mA at 5V Vgs with a quick look at the transfer curves I could determine rapidly that there wouldn't be an issue. If I could use a component only with the parameters listed under "test conditions" I would be very much restricted in the use of that component (not just this , I mean any), don't you agree?

 

You want to drive Vgs with -5V, and you hope to get low Vds at 100mA.The worst case threshold voltage is -4V when Ids=250uA and Vds=-4V. Selecting a part at random, you probably will get low Vds, I wouldn't count on it. Of course, I'm used to designing circuits that have to work with anything that meets spec.
Consider this, though: You design a circuit that has a 5V supply, and you order and pay for one or more of these parts to be used as a Vcc switch in this circuit. Chances are, the few you get will work - but they might not. Why not choose a part that is spec'ed for guaranteed Rds(on)@Vgs=-5V? There are quite a few parts available that will guarantee low Rds(on)@Vgs=-5V.
Fig.3 is pretty much worthless for low Vds analysis, because it is measured with Vds=-50V.

 

You want to drive Vgs with -5V, and you hope to get low Vds at 100mA.The worst case threshold voltage is -4V when Ids=250uA and Vds=-4V.

I see. The test condition for Vgs threshold is VDS = VGS.

How about figure 1? It tells me what current flows for a certain VDS and a certain Vgs.

At -4V VDS and -5V Vgs a current of 2A would flow (for the indicated pulse width). Or is that what you meant with "typical", i.e. it could very well be that the RdsON is much higher at this point and therefore the drain current lower...?

I understand that the RdsON at any Vgs voltage other than the specified is unknown.

Figure 1 should actually show worst case curves too, that would be useful.