Hi folks,
I am about to start playing with micro controllers to manage some alternative energy projects, just the control not any high voltage stuff.

The first thing that I want to do is manage my battery charging from PV's
I have a 12v system with circa 600W of panels, various ages and types.

I managed to get some p-channel FET's at a great price, low enough to parallel several on each 10A charging circuit thus reducing the effective RDS On they are IRF5305PBF.

I have never used P-Channel FET's although I got some great help here a while back with N-Channel devices for an avr I was struggling with.

Obviously I want, in fact need, to implement a high side switch which will be fed a PWM signal from the uP. It will not need to be particularly fast, but I appreciate that too slow a switching frequency will cause undesirable ripple on the batteries.

I know about totem pole drivers and will probably utilise this topology but having bought the FET's, thinking the driver would be far simpler than a bootstrap needed for N-Channel devices I realised that I hadn't thought it through.

Here is the problem …

My PV's could float at anything up to 24v with no load.
VGS Max is -20 with -10 being the figure used to specify RDS ON
I am assuming that I probably don't want to subject the gate to much above -15 with -12 being the target.

When the device is on there isn't a problem, assuming -15 is OK, because the PV voltage will drop to circa 14 but I am worried that when I first pull the gate low, before the device conducts fully, I will be stressing the gate to the point that it will probably damage the device.

Is this correct? and if so is there a simple solution?
Would the solution below work or am I missing the point.

I am assuming that I need a rail that floats at S-12v and that the driver circuit would have to switch G between that and S in the same way as I would need to switch between 0 and 12 in an N-Channel low side circuit.

Am I correct?
If so could I use a zenner / resistor divider to generate this rail and add a cap to provide sufficiently low impedance for the gate drive during the switch transition?

Lastly, how do I calculate the current that my gate drive needs to handle from the gate charge figures and if that is in fact possible would it be symmetrical, charge being the reciprocal of discharge I mean.

I am assuming that the higher the impedance of the gate driver the longer it will take to switch, generating losses and more importantly heat. I am assuming that some amps for some time = some charge but I wouldn't have a clue how to work that out particularly as I suspect that the current in the gate will be inversely proportional the the charge at any given point.

Any help will be appreciated and please don't pull any punches, being wrong is how I learn.
Thanks in advance
Al

 

Can you post a circuit diagram?

 

Well this is the thought process ...

Standard common emitter totempole acting as follower.

zenner / resistor divider to limit VGS by holding the totempole bases 12 below G.

ULN203A, darlington line driver to pull the devider low or allow it to float.
(Note that the 2.7k and 10k resistors are internal to the driver stage and the transistor is actually a darlington pair)

The sqr source and diode are simulating the uP drive pin.

Result, I think ... inverted driver with controlled VGS and positive logic control.

Please feel free to pull it apart if it got it wrong.
Thanks
Al

 

I would remove the totempole transistors and connect the gate of the p-fet to the junction of the zener and 6.8k resistor, and see if that works.


PS some powerfets don't need a gate resistor, so you could omit the 6.8K and replace the zener with a 10k.

 

OohKay .... Why?

Isn't the whole point of the follower configuration, totem-pole or otherwise, to shift the gate charge quickly via a low impedance circuit.
Or am I missing something?

This works in sim, all be it a quick and dirty one, what I am unsure about is if the follower will drive hard enough and exactly where I should be decoupling.
Al least that is what I thought I didn't know, perhaps there is more!

Don't get me wrong I appreciate the input, its just that I don't understand it.

Thanks
Al

 

I didn't do any calculations, but the basic idea looks OK. Couple comments ...

(1) Your FET symbol is incorrect. You're using a P-channel MOSFET so you need the symbol with the arrow pointing out. Look up the datasheet for your part and you'll see what I mean.

(2) I've used this circuit before (but without the totem pole driver because I was using it as a power switch, not a PWM as you are). I usually use a resistor in parallel with the zener to act as a pull-up when the transistor (ULN2003) is off. It needs to be sized so that the gate of the MOSFET is pulled high enough to ensure its completely off. In other words is has to be a lot smaller than the 6.8K resistor.

 

Bad symbol got it thanks. I am using a quick and dirty sim applet and it is just what it served up when I asked it for a P Mosfet. I really need to learn Spice.

Good point RE the pull-up but I beg to differ RE the reference to ,making it much smaller than the 6k8.
Since that is connected to ground via the open collector output of the line driver it inst in play when the logic is low.

My sym is working but I suspect that it is not taking account of the base current.
Essentially it is telling me that if the zenner is connected to the base then the base voltage will be the same as the upper rail which cant be right.

What I need to know is how the totem pole is actually working, how to calculate the base current for a given input voltage and what if any current limiting resistance will be required to keep it all working.

I will have another go ...

I have added a schematic of the circuit in both states, modified as you suggest, well mostly, with the additional pull-up
The open collector PWM buffer is replaced with a switch for clarity.
All values are basically guesswork.

What I need to know is how to calculate / handle the base currents, I could have a go at actually designing something then rather than guessing.

=========================== Update ===========================
Looking back at some previous posts and answers I found an answer to a question I asked about an emitter follower arrangement.
Bill_Marsden explained to me in thread [ http://forum.allaboutcircuits.com/archive/index.php/t-42922.html ] that the input impedance of an emitter follower is the gain of the transistor multiplied by the impedance at the emitter.

Is this still true if the follower topology is NPN / PNP comon emitter totem pole?

More to the point would it also be true that the huge input impedance of the FET gate will cause the totem pole input impedance to be equally huge, apart from when it is charging and discharging?

If most of that is correct would I be better with a current limit resistor in the totem pole input or connected to the FET gate? I suspect the latter.

Al

 

1. You don't need the 2.2k.
2. Zeners have high capacitance, so turn-off will be slow.

Try the attached circuit. It uses the ULN2003A as a switched 10mA current source.
If your uP runs on 3.3V, change R5 to 160Ω.

 

Thanks Ron, I didn't know about the capacitance problem, but I think I need the zener, or at least something that will provide a fixed voltage drop.

The bottom resistor needs to be above the driver channel because the chip will be controlling several of these circuits.

The rational behind using a fixed voltage drop is to ensure that VGS remains constant at different PV voltages.

I need to turn the FET of with PV+ so that VGS is 0 or at least close to it.
However since PV+ could float as high as 24V when the FET is off pulling it to 0 is a little risky as VGS could go as low as -23.5V which is well above the rated max.

So... I need to pull the gate to PV+ - 12V, or there abouts.
This will ensure that the FET is turned on hard, VGS @ -12, but not stressed during the period when the PV+ is falling to meet the rising BAT+.

I would be very interested in an alternative to the zener that will offer faster switching but it will need to work in a smiler manner, preventing VG from be pulled below PV+ -12.

Thanks
Al

 

Thanks Ron, I didn't know about the capacitance problem, but I think I need the zener, or at least something that will provide a fixed voltage drop.

The bottom resistor needs to be above the driver channel because the chip will be controlling several of these circuits.

The rational behind using a fixed voltage drop is to ensure that VGS remains constant at different PV voltages.

I need to turn the FET of with PV+ so that VGS is 0 or at least close to it.
However since PV+ could float as high as 24V when the FET is off pulling it to 0 is a little risky as VGS could go as low as -23.5V which is well above the rated max.

So... I need to pull the gate to PV+ - 12V, or there abouts.
This will ensure that the FET is turned on hard, VGS @ -12, but not stressed during the period when the PV+ is falling to meet the rising BAT+.

I would be very interested in an alternative to the zener that will offer faster switching but it will need to work in a smiler manner, preventing VG from be pulled below PV+ -12.

Thanks
Al

Ah, I forgot that ULN2003A has all the emitters tied together.
If you had a separate transistor for each level translator, the circuit I posted would give you a constant 10V Vgs on your PMOS, independent of the supply voltage.

 

Constant are you sure ... when I ran a sim the PV voltage was affecting the gate voltage ... Oooo wait I had the resistor above the transistor/driver.

Fixed it now and as you said it seems to work, although my little sim is predicting a lower voltage than you suggest.

I will be using 2N3904 / 2N3906 for the totempole, they have an HFE of about 100 with low Ic.

I could ditch the ULN2003 and replace it with an additional 2N3904 for each driver.

My sim suggests 6.8k on the collector with that 1k on the emitter and 4.7k on the base will give a gate voltage of about PV+ -12.2.
I will build it on a breadboard to check and tweek.

Is there a name for this transistor configuration?
Could you explain to me why it works if my explanation below is not correct.

I can see that the sub-circuit produces a constant current within a wide range of rail voltages and I understand that this will result in a constant voltage across the top resistor with the transistor / resistor at the bottom dropping the rest.

Am I correct in assuming that as Ice rises it results in an increase of Ve, due to the resistor between there and ground.
This has the effect of reducing Vbe and therefore Ibe which results in increasing Vce as the transistor starts to turn off.

Thanks
Al

 

Your PMOS transistor will be fully on with Vgs=10V. Use a low-wattage 10V zener (e.g., 1N758). Put 3k in parallel, and use 1k from the zener to the collector of the ULN2003A. The simulation looks pretty good with these values.

 

Thanks, I think I will try both your suggestions, the transistor looks good as well as the update of my ULN2003 idea.

All the help is very much appreciated.
Al

 

Check out 74LS06 as an alternative to ULN2003A. You only get 6 inverters, versus 7 for the 2003, but Vce(sat) is about a volt lower with the LS06, which is important when the PV gets down to 14V.