Please help me with the question in the picture about pull-up and pull-down networks.

 

the image clearly shows table with 4 states. crowbarred (X) is unwanted state (shortcircuit since both networks are on) and therefore must be prevented.

if the pull up and pull down network are complements then yes, only two output stats are possible:

pull-down OFF and pull-up ON ---> output is "1"
pull-down ON and pull-up OFF ---> output is "0"

think of both networks as switches controlled by input.

 

Thanks. I read about crowbarred X and high impedance Z states before. However, knowing that complementary CMOS logic gates don't have these states make me surprised. I have never thought about that.

 

Remember, the "C" in "CMOS" stands for "complementary".

Strictly speaking, true a true CMOS circuit has complementary pull-up and pull-down networks and therefore does not support three-state logic. Of course, this strict interpretation didn't last long (it's doubtful it was every really meant to be taken strictly in the first place) and three-state logic was there pretty much from the beginning.

None-the-less, it's still good to understand why that word was used and what it means.

 

You can turn a standard 2 state 1 & 0 driver into a Z & 0 driver simply by leaving out the top P MOSFET.

"Open Drain" (or for historical reasons "open collector") give a clean way to directly wire together several outputs safly, yet allow one or more to simultaneously impose the resultant state.

It is also known as "wired OR."

http://en.wikipedia.org/wiki/Open_drain#MOSFET

 

C in CMOS means complementary as in that the techonology is using both P and N channel transistors on the chip, as opposed to NMOS logic for example.
This has nothing to do with the outputs being push-pull only. The chip being CMOS doesn´t mean that the top and bottom transistors of the output pair cannot be driven independently or even have one of them missing entierly, which allows for open drain and tristate outputs.

See this nand gate for example, http://en.wikipedia.org/wiki/File:CMOS_NAND.svg there is no output complementary pair, but rather four series-parallel transistors directly controlling the output.
Yes there could be an output buffer connected to the output of the nand gate, which would be made of complementary pair invertors, but this isnt necessary for the circuit to function and still be called cmos.

 

back in the old days, cmos gates and inverters were used in an analog mode too, using the voltage levels between 1 and 0, the outputs would follow thi input voltages. a bit distorted at higher levels tho.

 

Back in the old days I built a single channel of a home stereo:

Phono cartridge preamp
Tone controls
Class D "power" amp

All - as in 100% - CMOS inverters.

ak