Hi,
I have a question about calculating output impedance of common-source amplifier.
Here is part of lecture about common-source amplifier.
Source: http://whites.sdsmt.edu/classes/ee320/notes/320Lecture31.pdf

My question is about how to calculate output impedance.
Output impedance of the circuit is defined as follows:
\(Z_{out} = \frac{ V_{out} }{ I_{out} } \)
Then, why we need to use small-signal model to calculate it? I guess it is because that at the output there is only ac component, dc component is blocked by the coupling capacitor and this is why small-signal model is used here.
And there other ways to calculate the output impedance of the circuit not using small-signal model?

 

And there other ways to calculate the output impedance of the circuit not using small-signal model?

The small-signal model is nothing else than a VISUALIZATION of the voltage-current relationships internal to the transistor.
Thus, the output impedance of the transistor is always determined by the voltage-to-current ratio at the output node - independent on the graphical or mathematical tools you are using for calculation.

 

The small-signal model is nothing else than a VISUALIZATION of the voltage-current relationships internal to the transistor.

What did you mean with "internal" here? I think you meant it is the relation between voltage and current of small-signal (ac) component.

Thus, the output impedance of the transistor is always determined by the voltage-to-current ratio at the output node - independent on the graphical or mathematical tools you are using for calculation.

OK, I see. You meant that small-signal model is only a tool among others to get the the voltage, current of ac component.
In calculation of output resistance above, input voltage, Vsig is set to zero. What is the reason for it? I also read about this in two-port network but still don't understand.

 

What did you mean with "internal" here? I think you meant it is the relation between voltage and current of small-signal (ac) component.

The small signal model contains some parts (active, passive) that model the physical effects which take place within the device. And these effects are modelled by "internal" voltage-current relations.

In calculation of output resistance above, input voltage, Vsig is set to zero. What is the reason for it? I also read about this in two-port network but still don't understand.

In order to simulate the output resistance you insert a current into the output node and determine the resulting voltage. Then, Ohms law gives you the desired result.
However, in this case the transistor must not produce an output signal caused by any input. Thus, Vsig must be set to zero.