Oscillator Circuit Limiter

Thread Starter

jp1390

Joined Aug 22, 2011
45
Hi all,

I just have a question regarding this popular limiter circuit. It is used to control the amplitude for oscillators but I am confused how it actually establishes control.



So when the input is small, the output will grow fast (larger slope) until it reaches the limiting voltage L+/-, but I still don't understand how this prevents the oscillator from decaying or growing.

Could anyone lend a hand in the explanation?
Thanks,

JP
 

t_n_k

Joined Mar 6, 2009
5,447
Another perspective is to regard the circuit as an amplifier with non-linear gain which is dependent on signal amplitude. Up to a certain input signal range there is a higher gain. For input signals greater than a certain threshold the gain reduces.

Sustained oscillation in feedback oscillators depends upon two key factors. Overall feedback loop gain and phase shift. With an amplifying device (such as an op-amp) operating in oscillator mode, the output signal amplitude excursions can increase unbounded virtually up to the output saturation limits of the amplifier. In that situation the gain falls rapidly and further amplitude increases stop abruptly - leading to output signal distortion near the peak excursions. In the amplifier limiter case shown in the post, the transition from higher to lower gain is made much less abrupt or "softer". This gives less amplitude peak distortion. At the same time, the reduced gain value alters the closed loop feedback conditions, thereby reducing the tendency to increasing oscillatory behavior. Any tendency for the amplitude excursion to reduce significantly would be counteracted by an increase in gain as the signal tended to fall below the transition threshold.

The attached image shows the limiter configured as a Wien Bridge Oscillator.
 

Attachments

Last edited:

Thread Starter

jp1390

Joined Aug 22, 2011
45
Another question I have is when they break up the Wien Bridge oscillator and solve for the loop gain.

They break the connection between the parallel cap/resistor to the non-inverting input of the op-amp and set that as the output while putting an input source connected to the (now free) non-inverting input.

Why is this so?

Thanks
 
Top