operational amplifier design

Thread Starter

jsnx

Joined Mar 17, 2022
21
Hello,

I'm trying to design an one stage OP AMP made of a differential pair, a current load and a current mirror as shown in the picture ( the first stage only, I didn't include Q7 Q6 and Compensation capacitance)
1649783510155.png

I designed the circuit to have a gain of 100V/V, a slew rate of 2V/µs, aGWB of 2.5MHz and for a load of 10pF. I followed the gm/Id methodology to size my transistors and when I plot the gain and the phase I get the following curves
1649783607402.png

Where can the problem be?

Thank you in advance for your help.
 

crutschow

Joined Mar 14, 2008
30,080
How you connecting the circuit to make that measurement?
You have to close the loop with DC feedback to measure its parameters, otherwise it likely will sit at one of the power rails.
 

Thread Starter

jsnx

Joined Mar 17, 2022
21
How you connecting the circuit to make that measurement?
You have to close the loop with DC feedback to measure its parameters, otherwise it likely will sit at one of the power rails.
I'm looking for the open-loop gain so I've put an AC source on the non-inverting input and I have a feedback loop on the inverting input with a high resistance (1 TOhm). The circuit is similar to this one.
1649784397196.png
 
Top