Hey guys and gals Im currently trying to gain some practical skills with the PIC24 microcontroller and im having trouble understanding some concepts i need to know before i start attaching components to my system.
So to my understanding a GPIO pin is normally driven by a CMOS network with a PMOS pullup network and a NMOS pulldown network. With maximum rating at that pin of 4mA and 5.6V
When I apply a 0 to this network it connects the power supply voltage to the pin and outputs a logic high(3.6V) and current drains out of the pin.
When I apply a 1 to this network it connects ground to the pin and outputs a logic low and current drains into the PIC.
For an open drain configuration we are disabling the PMOS pullup network and instead setting up our own pull up network external to the microcontroller. The logic behind this from what I understand is so that we can get a greater voltage available to a load than the power supply of the microcontroller. But again this would have to be limited to 5.6V and 4mA at the pin right?
If you can see flaws in the logic please explain!
Thanks
So to my understanding a GPIO pin is normally driven by a CMOS network with a PMOS pullup network and a NMOS pulldown network. With maximum rating at that pin of 4mA and 5.6V
When I apply a 0 to this network it connects the power supply voltage to the pin and outputs a logic high(3.6V) and current drains out of the pin.
When I apply a 1 to this network it connects ground to the pin and outputs a logic low and current drains into the PIC.
For an open drain configuration we are disabling the PMOS pullup network and instead setting up our own pull up network external to the microcontroller. The logic behind this from what I understand is so that we can get a greater voltage available to a load than the power supply of the microcontroller. But again this would have to be limited to 5.6V and 4mA at the pin right?
If you can see flaws in the logic please explain!
Thanks