Open drain configuration

Discussion in 'General Electronics Chat' started by Manmeet Singh, Jul 11, 2010.

  1. Manmeet Singh

    Thread Starter Active Member

    May 21, 2008
    Hey guys and gals Im currently trying to gain some practical skills with the PIC24 microcontroller and im having trouble understanding some concepts i need to know before i start attaching components to my system.

    So to my understanding a GPIO pin is normally driven by a CMOS network with a PMOS pullup network and a NMOS pulldown network. With maximum rating at that pin of 4mA and 5.6V

    When I apply a 0 to this network it connects the power supply voltage to the pin and outputs a logic high(3.6V) and current drains out of the pin.

    When I apply a 1 to this network it connects ground to the pin and outputs a logic low and current drains into the PIC.

    For an open drain configuration we are disabling the PMOS pullup network and instead setting up our own pull up network external to the microcontroller. The logic behind this from what I understand is so that we can get a greater voltage available to a load than the power supply of the microcontroller. But again this would have to be limited to 5.6V and 4mA at the pin right?

    If you can see flaws in the logic please explain!

  2. kdillinger

    Active Member

    Jul 26, 2009
    How are you going to disable the pMOS in the microcontroller? To my knowledge you cannot disable one particular transistor. Although, I do recall that in some MCU's you can set the output to Hi-Z which would allow the output to float to whatever voltage you needed.
    So are you going to toggle between Vol and Hi-Z? If so, you can do this provided you do not violate the absolute maximum ratings which typically dictate breakdown voltages of the silicon process the device is manufactured on.
  3. Manmeet Singh

    Thread Starter Active Member

    May 21, 2008

    For the PIC24 I was taught that there are C functions that allow this to happen for a specificed pin. You would be switching between providing a path to ground by having the NMOS transistor acting as a switch and being on or you would have the NMOS transistor act as it was open therefore being a high impedance path and deterring the current to the load. I guess im kind of answering my own question here lol but I guess I just wanted reassurance of my logic.
  4. Ghar

    Active Member

    Mar 8, 2010
    I recently saw a guy using a micro that lets you define which outputs are "push pull" vs "open drain" via a register.
    When we compared it the behaviour didn't really make sense to me, but anyway the point is it is an option in some chips.
  5. SgtWookie


    Jul 17, 2007
    As far as I know, Microchip PIC uC's have their I/O pins protect from ESD by using clamping diodes. This means their I/O range is limited to a range between Vss and Vdd. Excursions outside Vss/Vdd are unwise, and will likely result in a fried (burned up) uC.

    If you wish to control an external device who's range exceeds the Vdd or Vss of the uC, I suggest that you use an external component to do so, such as a transistor or MOSFET.

    PIC uC's are relatively inexpensive, but if you destroy an I/O pin, you'll wind up having to replace it. External transistors are far less expensive than the uC itself, and really don't take up a lot of board space.
  6. Ron H

    AAC Fanatic!

    Apr 14, 2005
    Open drain also allows multiple outputs to be connected together, with one common pullup (usually a resistor), thus getting a logic minus OR function.
  7. Manmeet Singh

    Thread Starter Active Member

    May 21, 2008
    I have been trying to understand why it is we need to use transistors or mosfets or relays and the process of looking through the other options and there limitations is helping me appreciate why these components are used.

    So far what I have been able to conclude is that in a normal CMOS setup for a pin we can only drive components that have a <=l voltage rating to the internal voltage of the uC and a current rating <= to the max rating of that pin. We can step things up somewhat by having disabled the PMOS network and having a open drain configuration which allows us to have a greater voltage then the internal voltage of the uC but still limited by the max available voltage and current rating of the pin. So in conclusion if we have a component that needs greater voltage or current we need to use BJTs or MOSFETS that have there gates controlled by a smaller voltage or current of the uC to enable a larger one for the device.