# Op-amp simulation help

#### geft

Joined Dec 8, 2011
19
For a lab experiment we are required to build an op-amp circuit according to instructions provided. However, the instruction given is rather vague and a lot of steps are omitted. I've pretty much completed the circuit, but for some reason the gain is only in the thousands. The specifications demand at least 500k Av while consuming less than 5mA. Here is how my circuit looks like. It's made up of a current mirror, Widlar circuit, common emitter voltage amplifier as well as a common collector stage for the buffer. Vout is measured in the output stage. Is there anything wrong with the circuit?

#### crutschow

Joined Mar 14, 2008
33,325
The circuit appears OK. I did an LTspice simulation of the circuit which indicated a DC gain of over a million. I measured the gain by doing a DC sweep of the input over a range of plus to minus 300μV in 1μV increments. The point at which the output swings from negative to positive saturation is the linear gain region. You divide the output swing by the input voltage change over the swing to get the DC gain.

The gain is so high it's difficult to measure the open loop gain at a single bias point, especially since there is a slight (couple hundred microvolts) DC offset in the circuit, thus I used a DC sweep to measure the gain.

How did you measure the gain?

I noticed you show a 3.5mV offset bias at the input which will completely saturate the circuit and give a very low apparent AC gain.

#### geft

Joined Dec 8, 2011
19
Thank you very much! I did a sweep from 9V to -9V at 1mV increment, and then tracing the Vout over Vos. The gain is therefore the slope of the swing I believe. The 3.5mV was obtained from the resulting plot. Since the slope was relatively low, I thought I had to do an AC sweep, which results in very low gain like you said.

I just checked and it's indeed well over 500k. How does changing the range affect the apparent gain? Also, what does it mean when the specification says the total current consumption has to be less than 5mA. Does that refer to the current through the batteries? Or is it the current through R1?

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#### crutschow

Joined Mar 14, 2008
33,325
1mV is too large a sweep increment to accurately resolve the high gain value. It takes less than 15μv to swing the output rail to rail. That's why I used a 1μV increment. The gain is indeed the slope of the output swing in the active region divided by the slope of the input swing over the same interval.

The total current consumption is the current from the supplies. My simulation showed about 5.6mA maximum so you appear to be slightly over the limit.

#### geft

Joined Dec 8, 2011
19
How do I make sure the current is less than 5mA? With no offset bias, the current is less than 5mA, but with the bias added, it's always exceeded.

#### thatoneguy

Joined Feb 19, 2009
6,359
R1 and R2 are the only apparent choices to lower consumption, but that will mess up the gain, which you have to spare.

#### crutschow

Joined Mar 14, 2008
33,325
R4 can also be increased to reduce current consumption.

#### Ron H

Joined Apr 14, 2005
7,014
R4 can also be increased to reduce current consumption.
But R4 is already to large to drive practical grounded or cap-coupled loads. A push-pull emitter follower output stage would be more practical.

#### thatoneguy

Joined Feb 19, 2009
6,359
Making the input stage out of FETs may work, but that would require a major re-work of the amp. Though it'd get your current down a good deal.

#### crutschow

Joined Mar 14, 2008
33,325
Making the input stage out of FETs may work, but that would require a major re-work of the amp. Though it'd get your current down a good deal.
A FET does not necessarily use less current then a bipolar transistor. In both cases it depends upon how they are biased. FETs do require negligible gate current as compared to the base current of a bipolar transistor, but the base current is a small part of the current a bipolar transistor uses.

#### thatoneguy

Joined Feb 19, 2009
6,359
Just a thought, when 600μA needs to be cut, any little bit is a pretty big help.

#### Ron H

Joined Apr 14, 2005
7,014
I simulated the circuit, using the models I have in LTspice. I changed R1 to 10k, to get the supply currents down to about 4.7mA. It would make sense to use a scaled-down transistor for Q1 (if this was an IC), or, in this case, multiple units in parallel for Q10, eliminate R2, and use a larger value for R1, to reduce the current wasted through R1 and Q1. One disadvantage of using multiple transistors in parallel for Q10 would be increased capacitance on the Q10 collector node, which would reduce the bandwidth.

You can run operating point and AC sims with this circuit. I get input offset voltage of 160uV and open loop gain of 125dB.

Note that geft has inn and inp reversed. His inn is actually the noninverting input, and vice-versa.

As I said previously, I recommend push-pull emitter followers for the output stage.

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