http://www.allaboutcircuits.com/vol_6/chpt_6/2.html

I thought that an op-amp's output was given by E=A(V[2] - V[1]), where E is the output EMF, A is the open-loop gain, and V[1] & V[2] the input voltages, ignoring the affects of input and output impedances. So basically the output is proportional to the difference in input voltages.

I've read that for a comparator you can have a set voltage on one input, and a varying voltage from a sensor on the other input, and when the sensors voltage exceeds the set voltage, the output will be high, while when it is below, the output will be low, such that it can be used to trigger a relay or something.

I can understand the fact that when V[2] > V[1], E>0, and when V[1]>V[2], E<0, but alot of things I've read about this so far, seem to give the impression that when you have the condition V[2]>V[1], the output will be a

*steady*logic voltage (high), and when V[1]>V[2], you will have a

*steady*logic voltage (low).

I believe this is the principal behind ADC's, but what I don't get is why the output is steady for a

*changing*input voltage. If this satifies the equation:

E=A(V[2] - V[1])

and if V[2] = 2sin(t), while V[1] = 1V,

then the output should be proportional to 2sin(t)-1, which is still a varying signal.

I don't get it can anyone help? Thanks