See first figure attached for problem statement.
Second figure for my "attempt".
I can't figure out how to calculate the correct number of transistors for a given gate.
I figured well a NOT will require 1 CMOS transistor, and a NAND will require 2 CMOS transistors.
So if I do a NAND followed by a NOT I'll get an AND.
So a 2 input AND would be 3 transistors by this logic.
Then a 4 input AND would be 6 transistors, but the answer says it's 10 transistors.
Similarily, a NOR will require 2 CMOS transistors and if I follow this NOR by a NOT I'll get an OR.
So a 2 input OR would be 3 transistors.
Then a 3 input OR would be ? transistors.
I need a better method for finding out how many CMOS transistors are required for each logic operation.
Any ideas/suggestions/tips/hints?
Thanks again!
Second figure for my "attempt".
I can't figure out how to calculate the correct number of transistors for a given gate.
I figured well a NOT will require 1 CMOS transistor, and a NAND will require 2 CMOS transistors.
So if I do a NAND followed by a NOT I'll get an AND.
So a 2 input AND would be 3 transistors by this logic.
Then a 4 input AND would be 6 transistors, but the answer says it's 10 transistors.
Similarily, a NOR will require 2 CMOS transistors and if I follow this NOR by a NOT I'll get an OR.
So a 2 input OR would be 3 transistors.
Then a 3 input OR would be ? transistors.
I need a better method for finding out how many CMOS transistors are required for each logic operation.
Any ideas/suggestions/tips/hints?
Thanks again!
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