Dear members ,
Please see the enclosed attachment.
This is NOT GATE implemented through NPN transistor.
I framed the equation for the collector emitter side as follows
Vs = IcRc + Vce
where Vs is source voltage, Ic is collector current and Vce as the voltage drop across collector emitter.
I dont understand the following concept
When the input is 0, the transistor is in off state, so there wont be collector current so Vs = Vce. , the out put will be 1. Similarly when the input is 1 the transistor is saturation state so the output will be 0
Please throw some light on these concepts and let me understand how NOT gate is implemented using NPN transistors
Please see the enclosed attachment.
This is NOT GATE implemented through NPN transistor.
I framed the equation for the collector emitter side as follows
Vs = IcRc + Vce
where Vs is source voltage, Ic is collector current and Vce as the voltage drop across collector emitter.
I dont understand the following concept
When the input is 0, the transistor is in off state, so there wont be collector current so Vs = Vce. , the out put will be 1. Similarly when the input is 1 the transistor is saturation state so the output will be 0
Please throw some light on these concepts and let me understand how NOT gate is implemented using NPN transistors
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