Hi I was wondering if someone could explain to me how to draw a timing diagram for a not gate who's output is feed back to its input, im not sure why it should oscillate, if i have the not gate with a delay of 1 unit, and i take to reference points, S (at the gate input) and Q at the gate output feed to an external output, should the two waveforms be the same or should they differ in phase, i am not sure how to look at this.

This is not for any homework solutions it is required knowledge that I need to understand for my digital design course that i absolutely suck at.

 

A single CMOS schmitt trigger type inverter will reliably oscillate with the output fed back to the input - usually through an RC network to control the frequency. Essentially there needs to be a propagation delay from the inverter input to output. The delay determines the period of oscillation. If there are no external delay elements in the feedback path then there still exists the possibility of self oscillation occurring.