Nor gate implementation for some given logic

Thread Starter


Joined Sep 18, 2011
Hey guys was wondering if any of you could field a couple of basic questions regarding this nor gate circuit im trying to make. Basically I have 3 IP variables HS, RIM, MF and four OP's FST, FWD, REV, ERR. The boolean that I have for them I am very confident in.

I was hoping one of you could take a look below at the attachement and answer a few related questions. For the first one Im just asking if tying my output high will cancel out that one NOR gate....which I don't believe it will. I ask because a buddy of mine said he only had to use 7 NOR gates, while im stuck here using 10 NOR's. Originally I worked out the boolean in terms of AND and just stuck in and reduced what I could to get 10 NOR gates. Whats the least possible amount I can use here? Can you really get away with 7 NOR's in my scenario?



Joined Mar 9, 2011
I end up with 7 as well - once you redraw the diagram using NOR only, look for shared nor inverters that can be "moved out" by which I mean that you end up inverting same input twice for two different gates, so you can use one inverter earlier and take output from it. It is about simplifying the signal coming in.

p.s. sorry i am unable to post a pic right now....