1. Vgs=9V (g + lead,d - lead) and Vdg=-9V (g - lead,d + lead)
2. switch
3. Vgs=-97mV (g + lead,d - lead) and Vdg=12V (g - lead,d + lead)

nmos is irfz44n Vgs +-20V max Vdg r20kΩ =55V max nothing about (-)

*excuse me I not local
*excuse me hangover
*excuse me ....
please ideas (no wiki)

 

1.) You can't apply a negative VDG with a positive VGS without having a negative voltage to the drain/source which will cause the body diode to conduct. In that case it will fry if there isn't anything else limiting the current. No matter what voltage you apply to the gate under this situation the Mosfet will never turn off because the FET itself isn't on, it's the body diode that is conducting.

3.) There is nothing wrong with applying a negative VGS to a nfet as long as the drain is positive relative to the source and as long as the gate to source voltage stays under 20 volts (positive or negative doesn't matter) A negative gate voltage (probably higher than -96mv) will actually likely decrease leakage current slightly, but it will take longer to switch to an on state because of the extra charge on the gate capacitance.

 

SIM allows but whether it actually will work

no switch in the sim .
I'm sorry that Picture took time.

*excuse me I not local
*excuse me hangover
*excuse me ....
please ideas (no wiki)

 

Please post the schematic files the number you intially refrenced don't match what those graphics show, and I can't tell off the cuff what it means without the actual LTspice files.