Hi all .. I'm new to VHDL and confused with this design when Acknwledgement= '1' and clk='1' then count should be count+1; and when Acknwledgement= '0' my total counted value should be assigned to the 'output' irrespective of clk and after that resetting count='0'. can anyone help with this. Thanks in advance.
Code ( (Unknown Language)): library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity acknw is Port ( acknw: in STD_LOGIC; clk : in STD_LOGIC; output : out INTEGER RANGE 0 To 15); end acknw; architecture Behavioral of acknw is begin process(clk,acknw) variable c : INTEGER RANGE 0 To 15 ; begin if(clk'event and clk='1') then if(acknw='1') then c := c+1; output <= c; else c := 0 ; output <= c; end if; --when reset equal to '1' make count equal to 0. end if; end process; end Behavioral; But I need the output value has integer value like 120 or 300 etc., can anyone guide me !!!
Iam getting the output value in binary format like 101,111 but I need this value as 5,7 i.e., the counted clock value . How this can be made. Thnks in advance
How are you looking at the output? Given that VHDL is used to describe digital systems, the binary representation of the number seems reasonable.
To be output where? How are you looking at the number, through a simulator? What are you using to run the vhdl?