hello everyone, i just learned about this site and wanted to see if i can get any help about my current project.

i recently made an opamp with cadence for a project. i have used the basic topology (two-stage = differential amplifier + common source - attached with a current generator). now for my questions:

1) i was able to meet all the specs except for the slew rate. i am not planning to work on it any further though, i did everything i can but the layout simulations doesn't give me the slew rate i want although the schematic simulations does. My question is, how bad it is for an op-amp to have low slew rate? How it effects the usage?

2) my most annoying problem, every exaple i saw and every text i read says that the phase margin of the opamp stops at -180ô, however mine goes beyond that up to -350s. is this a problem or can i neglect this?

3) there is a huge power consumption difference between my schematic and layout simulations that i can't explain. only difference between is that in schematic, the R next to compansation capacitor is 20 kohm and the same R in layout is 30 kohm. schematic simulation displays a power consumption of 400mW whereareas, layout simulation displays 100mW confused What might be the reason for that? (layout extraction for simulation is C_only btw)

thanks to all who bothered to read =)

 

Can you provide a schematic of your op-amp design?

hgmjr

 

yes, here it is =)

sorry for the low quality, i can feed anyone interested with more info...

 

A low slew rate limits the frequency range that the opamp can handle. A 741 has a 0.5 V/usec slewrate, (IIRC), and has trouble at at about 9 kHz. This means it is pretty useless for most audio applications. Low slew rate does decrease the probability that it will be unstable under most load conditions.

 

1) i was able to meet all the specs except for the slew rate. i am not planning to work on it any further though, i did everything i can but the layout simulations doesn't give me the slew rate i want although the schematic simulations does. My question is, how bad it is for an op-amp to have low slew rate? How it effects the usage?

The full power bandwidth (FPB) is equal to SR/(2*pi*Av*Vpeak). What this means is that you will be limited to how much bandwidth you can ultilize depending upon your gain.
The op-amp will try to slew the output in order to reproduce the input albiet with a higher swing. As you have a little squiggle on the input, a high gain configuration will try to reproduce a larger output swing at the same frequency.
It is easy to understand that in order to avoid slew rate induced distortion (input sine wave will be an output triangle wave) that the op-amp must be able to slew fast enough to reproduce the input signal on the output at the same frequency with a high voltage swing.
Lower gains will increase your bandwidth for obvious reasons. The internal capacitor is a big culprit here.

2) my most annoying problem, every exaple i saw and every text i read says that the phase margin of the opamp stops at -180ô, however mine goes beyond that up to -350s. is this a problem or can i neglect this?

How are you measuring this and at what frequency does this happen? This does not make sense.

3) there is a huge power consumption difference between my schematic and layout simulations that i can't explain. only difference between is that in schematic, the R next to compansation capacitor is 20 kohm and the same R in layout is 30 kohm. schematic simulation displays a power consumption of 400mW whereareas, layout simulation displays 100mW confused What might be the reason for that? (layout extraction for simulation is C_only btw)

What settings are being used?