Need help with my Half-Bridge

Discussion in 'The Projects Forum' started by mashmohsen, Aug 4, 2011.

1. mashmohsen Thread Starter New Member

Aug 4, 2011
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Hi Guys,
I'm a newbie in this area and have a project for which I need to make an 200 Vac signal(f=100Hz) from a 3.7Vdc input signal.
As you all can see in the attached figure, a flyback converter has been used in the first-stage and then a half-bridge scheme in the second stage. Can you tell me how I can figure out the value for L?
My capacitors at the output are both 22nF and the desired output voltage has been shown there.
I also have problem in driving the mosfet switches in case of Ql and Qh. In fact I'm trying to simulate the 2nd stage in Pspice which you can see in the second figure. Can you please hele me driving my Mosfets?

2. t_n_k AAC Fanatic!

Mar 6, 2009
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Notionally resonance occurs at

$\omega=\sqrt{\frac{1}{LC}-\frac{R^2}{4L^2}}$

with R=inductor series resistance. C in this case is twice the half-bridge capacitor value. If C_half_bridge=22nF then C=44nF in the formula.

But you may not actually want resonance condition - you probably need an operating frequency something like √2*f0. I'm not sure what it should be.... The circuit 'Q' must have some importance in the design.

If the operating frequency is 100kHz you might then use f0=70kHz.

Using a different device (IRF530) and faster diodes (BYV29-500) I get output per your requirement with L=100uH and the bridge caps C= 18nF at 100KHz. The inductor damping resistor was set to 56Ω.

Based on the aforementioned formula this setup has an f0=71.1KHz. The Q would be around 1.

Regarding your FET drive - for simplicity of simulation just put the upper FET drive source as an ungrounded (floating) waveform generator across the FET gate and source terminals as per the lower FET drive.

Edit:

Changing R to 2ohms gives a Q of about 26 and new f0=84KHz. Concurrently shifting the operating frequency to 125KHz gave an output from 0-200V per your requirement - also with a better sinusoidal characteristic than obtained earlier.

So with some logic - shift the resonant frequency down by the same factor (125/84 or ~1.5) for 100kHz operation. This would give f0=67KHz. A change of (84/67)^2=1.57 in inductor L would give this shift in f0. A new L=157uH satisfies the requirement at 100KHz as resolved in my subsequent simulations. With R=2 ohms, Q would be about 33 which I'm not sure is achievable in practice.

Even allowing Q to fall to a significantly lower value by increasing R doesn't dramatically change things - perhaps even improving circuit stability with the additional damping. Setting R=15ohms (Q=4.4) still met the design goal.

Last edited: Aug 5, 2011
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3. SgtWookie Expert

Jul 17, 2007
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For V2, you are using 0v and 5v for low and high output; but your MOSFET is a standard-level MOSFET that requires Vgs=10v to be fully turned ON. You either need to use 0v and 10v, or select a logic-level MOSFET.

This also applies to V7, once you get its' negative terminal connected to the MOSFET source terminal instead of GND (R9 should also be connected between the gate and the source terminal instead of gate and GND).

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4. mashmohsen Thread Starter New Member

Aug 4, 2011
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Thank you guys for your responses. I still have problem simulating the second stage. I don't know why my output is an AC with amplitude aroud 3 volts. Another problem is that I want the output to have 100 Hz frequency. ( Now the frequency of the output is the same as the switching frequency which is around 100 kHz)
The output sinosoidal wave now is changing from 98v to 102 v (I want it to be from 0 ~ 200V)

5. t_n_k AAC Fanatic!

Mar 6, 2009
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Probably still the two issues need exploring

1. Insufficient or incorrect gate drive

2. Selection of resonating elements - L, C & R

Using your FET & diode type I get a result ~0-200V 100kHz with L=68uH, C=22nF & R=7.5Ω (even closer with 6.8Ω). Output measured across top or bottom capacitor.

Have attached the schematic that "worked" in my simulation. Gate drive not optimized.

I also suspect one should be wary of operating this circuit near resonance (as above ) - the loss in the (nett) damping / parasitic (?) resistance may become significant / unsustainable. Is the 5 ohm R2 in your simulation schematic specifically chosen?

Sorry - I'd also missed the point that you want the desired output voltage 0-200V to be at 100Hz rather than 100kHz. In that case you'll most likely need a PWM (100kHz carrier) control sub-block for the switching - as implied in the original schematic.

I'd also keep in mind that the 1N4002 diode may not be the best option for this application - you'll perhaps need a fast recovery diode. I'm not sure if the FET [IRF150] has an integrated reverse diode or not....? Just checked the IR data sheet and it seems that it has. So the external anti-parallel diode may be unnecessary. I also note that BVDSS=100V which will probably not meet the requirement in this application. A BVDSS much better than 200V is possibly more indicative.

So this is quite a complex problem with various matters needing careful attention.

Is the actual point of all this work really only to produce a 0-200V 100Hz sine wave from 3.7V DC?

• H bridge.pdf
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Last edited: Aug 6, 2011
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6. mashmohsen Thread Starter New Member

Aug 4, 2011
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t_n_k,
thanks for your responses. In fact I have to say that I'm exactly going to produce 0-200V 100Hz from 3.7 Vdc.
In the first stage as you know I'm just going to produce the 200Vdc and in the second I'm going to make it AC.
About the R2, I have to say it is not specifically chosen , I just put it there since I believe there would be a resistance regarding the Inductor L2. It may even be less and around 1Ω.
About the PWM, do you have any idea of what is the good frequency for PWM to produce a 100HZ output?
I guess for the MOSFET I have to use something like IRF740. DO you think it is important to have IRF150 instead just for simulation purpose?

7. t_n_k AAC Fanatic!

Mar 6, 2009
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You will need to set your L & C in particular at values consistent with 100Hz rather than 100KHz. You would be looking at values much greater than the 50uH and 22nF you initially chose.

Then you will pulse width modulate the 100KHz carrier to produce a 100Hz fundamental sinusoidal waveform.

8. mashmohsen Thread Starter New Member

Aug 4, 2011
7
0
I think I need to explain more about the circuit. The first part is a boost converter as you see, The second part should produce a unipolar sinusoidal out put AND recover charge from the load. The out put signal should have a 100 Hz frequency and the 22nF load capacitors are used as my actual load equivalent (so I cannot change them)

9. mashmohsen Thread Starter New Member

Aug 4, 2011
7
0
Guys

could you please send the simulation file for me? I could not get the results that you are talking about from my circuit. (I just have a signal with 20 Vpeak-peak and 100 Khz frequency)