Hi all,
I am trying to teach myself about PLL, and I am trying to start by building a known design. So I decided to build a PLL using the 74HC4046 chip from NXP.
http://www.nxp.com/documents/data_sheet/74HC_HCT4046A_CNV.pdf
In page 31 of the spec sheet, it has a sample design, which I bought the parts, and put it together.
After I put all the blocks together on a breadboard. this is what I am seeing at the F out:
http://www.flickr.com/photos/52479207@N05/6218529723/
what is going on? it looks like as if the filter is not filtering out all the higher frequency? that it's not locked? but why?
The VCO block checked out by itself; I varied the V in between 0 to 5 volts and was able to get a linear graph between the Vin and Fout on the Excel and get the expect value of 2.6e6 r/s/V for the K vco block.
The frequency divider block checked out by itself; i was able to varify the division ratio to divide by to be either 20 or 30. so the Kn will be either 1/20 or 1/30
I varified the crystal oscillator/divider pair that by itself it generated a signal = 99.9khz going into the PLL loop as F in, using a different crystal and divider that i've already got.
I don't have two fancy signal generator to sync the phase so i can't varify the functionality of the PFD; I assumed that it has the gain = Vcc/4*pi as listed since there's no external element that will effect its characteristics.
I don't have a spectrum analyzer to varify the filter. All I have is an oscilliscope. What I did is I connected the filter as it is, the input to an signal generator, set 1vpp as the amplitude, and the output to the scope, and I varied the frequency at the signal generator until I see the voltage drop down from 1vpp to 0.7vpp, and 20 log (0.7) = -3 dB and that's where the 3dB point is. From what I can see the 3dB point occurs around 180 Hz
So what have I missed? where else can I look to debug this circuit?
Also, on the topic of the filter. From what I understand, if the PLL is in the locked position, and the F in to the PD is 100 kHz, then that means it's 2nd order term will occur at 200Khz and that's where it should filter out. The filter transfer function,
H(s) = [1 + (1.5e-4)s] / [1+(1.1e-3)s]
looks like it has a pole around 140 Hz, and a zero around 1100 Hz (please verify). Can someone explain me why those values were chosen? why does it need a zero there so it flats out after 1100 hz?
Also, if all we care about is anything but the DC value, why even bother to filter just anything about 140 Hz? not simply design a filter where it's 3dB cut off is so low that it blocks out anything but the DC?
I am trying to teach myself about PLL, and I am trying to start by building a known design. So I decided to build a PLL using the 74HC4046 chip from NXP.
http://www.nxp.com/documents/data_sheet/74HC_HCT4046A_CNV.pdf
In page 31 of the spec sheet, it has a sample design, which I bought the parts, and put it together.
After I put all the blocks together on a breadboard. this is what I am seeing at the F out:
http://www.flickr.com/photos/52479207@N05/6218529723/
what is going on? it looks like as if the filter is not filtering out all the higher frequency? that it's not locked? but why?
The VCO block checked out by itself; I varied the V in between 0 to 5 volts and was able to get a linear graph between the Vin and Fout on the Excel and get the expect value of 2.6e6 r/s/V for the K vco block.
The frequency divider block checked out by itself; i was able to varify the division ratio to divide by to be either 20 or 30. so the Kn will be either 1/20 or 1/30
I varified the crystal oscillator/divider pair that by itself it generated a signal = 99.9khz going into the PLL loop as F in, using a different crystal and divider that i've already got.
I don't have two fancy signal generator to sync the phase so i can't varify the functionality of the PFD; I assumed that it has the gain = Vcc/4*pi as listed since there's no external element that will effect its characteristics.
I don't have a spectrum analyzer to varify the filter. All I have is an oscilliscope. What I did is I connected the filter as it is, the input to an signal generator, set 1vpp as the amplitude, and the output to the scope, and I varied the frequency at the signal generator until I see the voltage drop down from 1vpp to 0.7vpp, and 20 log (0.7) = -3 dB and that's where the 3dB point is. From what I can see the 3dB point occurs around 180 Hz
So what have I missed? where else can I look to debug this circuit?
Also, on the topic of the filter. From what I understand, if the PLL is in the locked position, and the F in to the PD is 100 kHz, then that means it's 2nd order term will occur at 200Khz and that's where it should filter out. The filter transfer function,
H(s) = [1 + (1.5e-4)s] / [1+(1.1e-3)s]
looks like it has a pole around 140 Hz, and a zero around 1100 Hz (please verify). Can someone explain me why those values were chosen? why does it need a zero there so it flats out after 1100 hz?
Also, if all we care about is anything but the DC value, why even bother to filter just anything about 140 Hz? not simply design a filter where it's 3dB cut off is so low that it blocks out anything but the DC?