Hi all,

I am trying to teach myself about PLL, and I am trying to start by building a known design. So I decided to build a PLL using the 74HC4046 chip from NXP.

http://www.nxp.com/documents/data_sheet/74HC_HCT4046A_CNV.pdf

In page 31 of the spec sheet, it has a sample design, which I bought the parts, and put it together.

After I put all the blocks together on a breadboard. this is what I am seeing at the F out:

http://www.flickr.com/photos/52479207@N05/6218529723/

what is going on? it looks like as if the filter is not filtering out all the higher frequency? that it's not locked? but why?

The VCO block checked out by itself; I varied the V in between 0 to 5 volts and was able to get a linear graph between the Vin and Fout on the Excel and get the expect value of 2.6e6 r/s/V for the K vco block.

The frequency divider block checked out by itself; i was able to varify the division ratio to divide by to be either 20 or 30. so the Kn will be either 1/20 or 1/30

I varified the crystal oscillator/divider pair that by itself it generated a signal = 99.9khz going into the PLL loop as F in, using a different crystal and divider that i've already got.

I don't have two fancy signal generator to sync the phase so i can't varify the functionality of the PFD; I assumed that it has the gain = Vcc/4*pi as listed since there's no external element that will effect its characteristics.

I don't have a spectrum analyzer to varify the filter. All I have is an oscilliscope. What I did is I connected the filter as it is, the input to an signal generator, set 1vpp as the amplitude, and the output to the scope, and I varied the frequency at the signal generator until I see the voltage drop down from 1vpp to 0.7vpp, and 20 log (0.7) = -3 dB and that's where the 3dB point is. From what I can see the 3dB point occurs around 180 Hz

So what have I missed? where else can I look to debug this circuit?

Also, on the topic of the filter. From what I understand, if the PLL is in the locked position, and the F in to the PD is 100 kHz, then that means it's 2nd order term will occur at 200Khz and that's where it should filter out. The filter transfer function,

H(s) = [1 + (1.5e-4)s] / [1+(1.1e-3)s]

looks like it has a pole around 140 Hz, and a zero around 1100 Hz (please verify). Can someone explain me why those values were chosen? why does it need a zero there so it flats out after 1100 hz?

Also, if all we care about is anything but the DC value, why even bother to filter just anything about 140 Hz? not simply design a filter where it's 3dB cut off is so low that it blocks out anything but the DC?

 

Maybe the high capacitance and high inductance of the breadboard is messing up the high frequency PLL? Try using a compact stripboard or pcb.

 

fout is the output digital frequency from the VCO. From your oscilloscope picture I can't tell what it is doing. You need to increase your sweep speed.
What is the measured fout frequency?
Why do you say it's not filtering out the higher frequency? What higher frequency?

 

From the looks of the scope shot, I would say that you have a lot of jitter -it is most likely because the loop is not stable, which might be corrected by "playing" with the loop filter.

Phase comparator 2 is an excellent wide range phase comparator, except that it is very sensitive to noise -any edge that comes along out of phase can through the whole circuit for a (excuse the use of the word) loop. Make sure your power supply is clean and there are no other noise sources.

 

Did you have short connections with a good ground between your 99.9kHz signal source and the PLL?
What is the voltage swing on that signal source?
Your vco output looks really noisy. Do you have a 100nF decoupling cap connected between vcc and gnd pins on the 4046?

 

@DickCapples:
Whether or not a PLL (or any circuit with feedback) is stable or not is actually one of the concepts I am trying to learn from this excercise. Maybe you can help me shed some light on this.

From what I know from reading on stability theory, as long as the poles are on the left plane, regardless where the zeros are located, then the circuit is stable (right?). For this PLL, the only thing that provides zeros/poles are the VCO (got pole in the orgin), and the filter (got a pole and a zero).

Maybe I need to go back to review my stability theory a little more, but I don't see anything in page 31 of that spec sheet where they did the math that tells me whether or not this is a stable circuit or not. It says in the spec sheet that the natural frequency deals with settle time, and the damping ratio determines the overshoot, as shown in Fig 33, but I don't understand how they determine the poles and zeros in such a way the PLL will be stable.

I am going to try build a math model on Matlab using their numbers and see what comes out of it tonight....

@ Ron,
Here's the picture of the PLL I build on a breadboard. The two circuit on the left are the oscillaor/divider that generates the 102.4 khz (sorry, thought it was 99.9khz), and the two chips on the right are the 4046 (PFD and VCO) and 4059 (the divider), I used the space in the middle for the filter.

http://www.flickr.com/photos/52479207@N05/6224897758/

Here's the screenshot of waveform coming out of the Osciallor/divider pair that feed the F in, measured at the end the wire that would have feed into the PFD of 4046.

http://www.flickr.com/photos/52479207@N05/6224398367/in/photostream

I don't understand what you mean by having the 100nF cap connect between vcc (pin 16) and the gnd (pin 8). How do i do that? why is that needed?

@Audioguru
Maybe i should re-do the whole circuit using solders and wires instead of breadboard?

 

From looking at the photo of your breadboard, there are no bypass capacitors (consistent with Ron H's comment about the 100 nf capacitor from VDD to VSS)!

Without bypass capacitors, the power supply and ground (VDD and VSS) conductors become part of the circuit at high frequencies. It is essential that you use decoupling capacitors to prevent noise from one part of the circuit from affecting other parts of the circuit. This is especially important with the '4046 phase comparator 2.

Not only should there be a 100 nf or perhaps a little larger capacitor between the VDD and VSS pins of each device, but a larger ("Bulk") bypass capacitor is probably a very good idea, especially since your voltage regulator is not on the board. Try 100 uf for the bulk capacitor.

The use of these solderless breadboards is fine for thing like lighting LEDs from batteries, but they are generally very poorly suited for use with high speed logic devices. It may be that because of the impedance of your VDD line ("ground") you will not be able to obtain stable operation with this solderless breadboard.

When considering circuit stability, you need to consider the parasitic components, such as the ground power supply connections.

 

I don't understand what you mean by having the 100nF cap connect between vcc (pin 16) and the gnd (pin 8). How do i do that? why is that needed?

Do a Google search on "decoupling capacitor" and read some of the articles that come up.

@Audioguru
Maybe i should re-do the whole circuit using solders and wires instead of breadboard?

You should build it on a board having a ground plane.

 

Do a Google search on "decoupling capacitor" and read some of the articles that come up.

... or read this ...

http://forum.allaboutcircuits.com/sh...ad.php?t=45583

 

Regarding the dynamic aspects of a pll, you have a loop filter there to enable you to have a decent - and controlled - response time or frequency characteristic (and phase error can come into it too). The loop filter, adding as it does an additional pole to the natural pole represented by the vco, makes the loop a second-order loop.

You can't just have 2 poles in a feedback circuit and expect it to be stable. You need to add the zero at a sufficiently low frequency that the circuit remains stable, and indeed offers a satisfactory damping ratio.

This book is all you need to become a pll expert:

http://books.google.co.uk/books?id=...l bandwidth natural frequency damping&f=false

(I hope that link works - the book is "Phaselock Techniques" by Floyd M Gardner, and I strongly recommend it as a purchase if you're serious about understanding plls.)

 

Each messy wire on your breadboard has series inductance (that blocks high frequencies)and picks up all kinds of interference like an antenna.
The capacitance between the rows of contacts on a breadboard are like short circuits at high frequencies.
So get rid of the breadboard.

Phase detector 2 of a 4046 PLL produces phase jitter. The signal at the "phase-pulses" output at pin 1 shows the pulsing phase changes.

 

How do I add a bypass capacitor between the Vdd and GND on the 4046A? they are at the opposite corner of the chip. do you mean adding a 0.1uF between the Vdd and GND rail (on the breadboard)?

I tried that on the breadboard just now and I am still seeing the same messy waveform as before. I think I am gonna ditch the breadboard and re-build the circuit with solder and board this time.

BEFORE I START PLAYING WITH SOLDERS, think i should take a few step back and work out the documentation/simulation first. So......

1) I am in the process to put together a drawing that shows how I plan to place each of the chips (on a standard prototype card, not PCB.... yet), and I will love it if you experts here can peer review that when it's done. Something tells me it's gonna be tricky to connect it such that minimize the wire length going between one chip to other, and to minimize any parasitic effect, cross talk, etc. Stay tuned.....

2) While I am figuring out the drawing, I also would like to run thru the math model of that PLL in Matlab, just to verify the stability, and to better understand the operation of the circuit. Does anyone here happen to have a PLL model in Matlab similiar to that PLL in the 4046 spec sheet that I can tweak the parameters with? Or have any documentation on running PLL in Matlab Simulink that could help me better understand the dynamics of poles and zeros?

Tom

 

If you can find perf board with ground plane, you'll have a better chance of making it work. A low-inductance ground really helps in reducing ground noise. Anywhere you have a GND on your schematic, connect it to the ground plane.
I use Twin Industries 8100 series boards. You can buy them in various sizes, and they are not cheap. You might be able to find a less expensive alternative.
I have also used single-sided copperclad board, and used a drill press and a pad cutter to make holes and pads for connections. There are other breadboarding techniques out there that incorporate a ground plane.

 

@Ron: I will be using a 7100 series board from Twin Industries. My budget is limited.

Here's the block diagram taken straight from the spec sheet, and a sketch that shows how I plan the layout the chips and wire them on my prototype board.

http://www.flickr.com/photos/52479207@N05/6244985185/in/photostream

Note this is not drawn to scale, though I did taken into consideration to minimize the distance between the input/output pins by position the chips the way it is shown. Also I omitted the wiring for setup the dividers (I will simply tight them to high's and lows as needed when I build it) and the values for R’s and C’s listed in the spec sheet just to save on clutter the drawing.

My questions:

1) How am I doing with the way I plan to lay out the chips? Any problems?

2) Notice those .1uF capacitors on each Vdd pin. Is that how to setup the decoupling capacitor?



3) what else am I missing?

 

No comments? so do I have the blessing from all the experts to build up the board as it is?

 

No comments? so do I have the blessing from all the experts to build up the board as it is?

You don't have my blessing. I wouldn't attempt it without a ground plane.
That doesn't mean you won't get it to work.