Need help sending 16 bits of data through serial on the DE0-nano-SOC

Hi everyone, I am currently working on a project that requires me to send 16 bits of data through a serial bridge (USB to TTL P2303) to python for further processing. I was also able to send 8 bits correctly over serial. At the moment I just want to test how I would send 16 bits. Currently I am using a process in VHDL that sets a flag for when the first 8 bits are transmitted and then transmit the following 8 bits which is altogether 16. At the moment only the first 8 bits are displayed in the serial monitor (I am using realterm) instead of the first 8 bits and second 8 bits. I have added my code below... My TX is added as a component and the transmission code is is that folder. I have done VHDL 3 years ago, so I apologize in advance if this code is scrappy. Any help would be appreciated. Thank you all for your time.

Ryan

MAIN FILE-----------------------------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity COMMS is
port( CLOCK_50,RST : in std_logic;
send : in STD_LOGIC;
q : out std_logic_vector(15 downto 0); --- output signal
UART_TXD : out std_logic);

END COMMS;


architecture MAIN of COMMS is
signal TX_DATA: std_LOGIC_VECTOR(7 downto 0);
signal TX_START: STD_LOGIC:='0';
signal TX_BUSY: STD_LOGIC;
signal TX_HALF: STD_LOGIC:= '0';
signal d : std_logic:= '0'; --- data bit input from feedback loop
signal state0: std_logic_vector(15 downto 0):= "0000000000000000"; --- Initial state
constant seed: std_logic_vector(15 downto 0):= "0000000000000001"; --- seed value

----------------------------------------------
component TX is
port( CLK :IN STD_LOGIC;
START:IN STD_LOGIC;
BUSY:OUT STD_LOGIC;
DATA: IN STD_LOGIC_VECTOR(7 downto 0);
TX_LINE:OUT STD_LOGIC);
end component;
----------------------------------------------
----------------------------------------------

begin
C1: TX PORT MAP(CLOCK_50,TX_START,TX_BUSY,TX_DATA,UART_TXD);


process(CLOCK_50,RST)
begin

if rising_edge(CLOCK_50)then
if TX_HALF = '0' then

if(TX_BUSY = '0') then
TX_DATA<= "00000000";
TX_START<='1';
TX_HALF <= '1';
else
TX_START<='0';
end if;

elsif TX_HALF = '1' then

if(TX_BUSY = '0') then
TX_DATA<= "11111111";
TX_START<='1';
TX_HALF <= '0';
else
TX_START<='0';
end if;
end if;
end if;
end process;

end architecture;

TX COMPONENT FILE--------------------------------------------------------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


ENTITY TX IS
PORT( CLK :IN STD_LOGIC;
START:IN STD_LOGIC; --start transmission
BUSY:OUT STD_LOGIC; --indicates if transmission is currently running
DATA: IN STD_LOGIC_VECTOR(7 downto 0); -- 8 bit vector we are sending over
TX_LINE:OUT STD_LOGIC); --Transmission line which goes out of FPGA to PC
END TX;

architecture arch_TX of TX is

signal PRSCL: integer range 0 to 5207:=0; --prescaler for the main clock
signal INDEX: integer range 0 to 9:=0; --To select which bit we are going to send
signal DATAFLL: STD_LOGIC_VECTOR(9 downto 0); --Consists of 8 bit data + start and stop bits
signal TX_FLG: STD_LOGIC:='0'; --A flag to start the transmission process
BEGIN
process(CLK)
begin
if rising_edge(CLK) then
if(TX_FLG = '0' and START = '1') then --new transmission starts only of no communication is currently running and the start signal is HIGH
TX_FLG <= '1';
BUSY <= '1'; --only if both conditions are true we set the TX_FLG to true and read the data and place it into the DATAFLL vector
DATAFLL(0)<='0';
DATAFLL(9)<='1';
DATAFLL(8 downto 1)<=DATA;
end if;

if(TX_FLG = '1')then --if TX_FLG is 1 we start sending data. For 9600 baud we use 50MHz/115200 = 434 for prescaler. This will give desired bitrate
if(PRSCL<5207)then
PRSCL <= PRSCL+1;
else
PRSCL <= 0;
end if;

if(PRSCL = 2604)then
TX_LINE<=DATAFLL(INDEX);
if(INDEX<9)then
INDEX<=INDEX+1;
else
TX_FLG <='0';
BUSY <='0';
INDEX <= 0;
end if;
end if;
end if;
end if;
end process;
end architecture;