need help on Program counter

absf

Joined Dec 29, 2010
1,968
I see, so you wanted to integrate your "MOV executer", ALU and Program Counter together?

Do you have any idea how this can be done?

Allen
 

Thread Starter

abhimanyu143

Joined Aug 25, 2014
211
yes but I don't understand how to connect program counter. as you said I need counter and mux to make program counter.
that's why I am asking you how to connect program counter ?
 

Thread Starter

abhimanyu143

Joined Aug 25, 2014
211
Simply because your address is 16-bit and your data is 8-bit. So you need to load a 16 bit address from 8 bit data bus in 2 clock cycles.

Allen
Program counter
Input signal
clock signal
clear signal
8 bit low address
8 bit High address

output signal
8 bit data signal

I think mux is use for following
low address means - output of multiplexer should (0)
high address means - output of multiplexer should (1)
when address mux is ( 0) then this is end of instruction and pc incremented for next address
when address mux is (1) then execute jmp or branch instruction

I don't understand how does 16 bit address load from 8 bit data bus ?
If there is any link or picture that define reason please attach link
 

absf

Joined Dec 29, 2010
1,968
I think mux is use for following
low address means - output of multiplexer should (0)
high address means - output of multiplexer should (1)
when address mux is ( 0) then this is end of instruction and pc incremented for next address
when address mux is (1) then execute jmp or branch instruction

I don't understand how does 16 bit address load from 8 bit data bus ?
If there is any link or picture that define reason please attach link
Wow, it has been almost a week and I dont see much progress in your PC design. Only wild guesses on what the muxes are doing, and speculating how 8 bit data bus can be connected to 16 bit address bus .....

As for any links for this, sorry no, I dont have any. Your google is as good as mine. I have never taken such a tedious task to design a similar mcu core like the 8051. Even looking at the verilog codes on the open-source code for 8051 gave me lots of headache, not to mention that I just started to learn VHDL on Altera platform. Actually you are more ahead of me as your are using Quartus II while I am still using MAX+II plus.

OK. enough blah-blah-blah. Have you taken my advice and look at the Architecture block of the 8051 on its datasheet? Here's one that I have simplify with MSPaint.... I removed all the unnecessary stuffs and left only the essential blocks for you to implement. I even removed the B register which I think you dont need it. If you can, you can even get rid of the crystal clock and replace with 2 LM555 - one for astable clock pulses and the other for monostable just to step the instructions.

8051 ARCH 1.PNG

I'll be taking a short vacation trip with family next week. After returning, I'll have a 3-week on the job-travelling to a remote town doing installation works. Dont be surprised if I just disappear from the forum for a while.

Allen
 
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absf

Joined Dec 29, 2010
1,968
One thing I must say..... To prepare materials for answering to all the questions asked by a poster is not easy. We take time to prepare the stuffs and sometimes have to flip through pages from my book-shelves and refer to past notes that I have taken from time to time.

So I hope the questioners would value the answers that we have given. BTW did you read through all the posts that you have asked about your 8051 core design? I am sure you've left out valued informations on all those posts. My master once told me that "If you cannot recognize the value of a diamond, you'll walk pass by one even if it is lying on the roadside in front of you; thinking that it is probably glass."

And dont say "Let's forget what we have discussed and just tell me this, this and this". I think that is rude and hurts people who tried to help you.

Allen
 
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Thread Starter

abhimanyu143

Joined Aug 25, 2014
211
And dont say "Let's forget what we have discussed and just tell me this, this and this". I think that is rude and hurts people who tried to help you.

Allen
I am really sorry Allen , I don't want to hurt someone. I said, because I want to understand simple PC and then I want to go for complex PC. I will remember. I will never say these word again
I'll be taking a short vacation trip with family next week. After returning, I'll have a 3-week on the job-travelling to a remote town doing installation works. Dont be surprised if I just disappear from the forum for a while.

Allen Allen

Ok , I Wish you a very happy journey
 
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Thread Starter

abhimanyu143

Joined Aug 25, 2014
211
Wow, it has been almost a week and I dont see much progress in your PC design. Only wild guesses on what the muxes are doing, and speculating how 8 bit data bus can be connected to 16 bit address bus .....

As for any links for this, sorry no, I dont have any. Your google is as good as mine. I have never taken such a tedious task to design a similar mcu core like the 8051. Even looking at the verilog codes on the open-source code for 8051 gave me lots of headache, not to mention that I just started to learn VHDL on Altera platform. Actually you are more ahead of me as your are using Quartus II while I am still using MAX+II plus.

OK. enough blah-blah-blah. Have you taken my advice and look at the Architecture block of the 8051 on its datasheet? Here's one that I have simplify with MSPaint.... I removed all the unnecessary stuffs and left only the essential blocks for you to implement. I even removed the B register which I think you dont need it. If you can, you can even get rid of the crystal clock and replace with 2 LM555 - one for astable clock pulses and the other for monostable just to step the instructions.

View attachment 78502

I'll be taking a short vacation trip with family next week. After returning, I'll have a 3-week on the job-travelling to a remote town doing installation works. Dont be surprised if I just disappear from the forum for a while.

Allen
I read the datasheet and I looked diagram. Its very tough for me I don't understand because there are timing and control unit , DPTR stack pointer involved in diagram
my knowledge : I understand registers , program memory , data memory , ALU, instruction Decoder and strugling with PC
I just want to ask you , can we start with counter and multiplexer? once I understand basic of PC , then I will go for 8051 PC

we have 16 bit program counter. we can load any bits. we can load Top four bits , middle four bits , bottom four bits , bottom 8 bits using multiplexers
just example for PC
for short jump (only load top four bit of PC )
for long jump (only load center four bit of PC)
for subroutine (load bottom four bit of PC)
upload_2015-1-10_22-12-23.png

My problem , I made red connection , I don't understand that connection

upload_2015-1-10_22-13-28.png
 

absf

Joined Dec 29, 2010
1,968
The PC design is considered almost complete. We would see if it is needed to add the DPTR (Data Pointer), PC incrementer and buffer later. The next step is the RAR, PAR and RAM to be added to your design.

For RAM you can use either 2114 (1Kx4 bits) or 6116 (2Kx8 bits). Do your connection with reference to the block diagram. Should be an easy task.

Allen
 
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absf

Joined Dec 29, 2010
1,968
I have done the schematics with Program Address Register, Ram Address Register and RAM (6116) added. But I want to see how you've done it before I post mine.

You can try to solve the problem on how to connect the PSW to the ALU as well. As the ALU only have the Cout flag, you have to find a way to implement the "zero flag" i.e. when the result of adding or subtracting 2 numbers = 0. That should be a piece of cake to you. Another thing is that your "Immediate Regiaster" is sitting in between the Data Bus and Accumulator; this would block any data sent from the ALU to the ACC. You have to do something about it too.

Allen
 
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absf

Joined Dec 29, 2010
1,968
I have got a lot of good design ideas from the link pointed by Ian Rogers of ETO here

http://www.bigmessowires.com/2013/08/27/custom-4-bit-cpu-schematic-and-control/

The Architecture is here

nibbler-architecture-v4.png

And the complete schematics is here

nibbler-schematic-v5.png

From this I am going to split your 8-bit ROM data into two halves. 4 bits for instructions and the other 4 bits for Imm data for MOV a,#imm and MOV R1,#imm; OR upper 4 bits of the 12 bit address on the JMP instruction.....

So much for now until I return from my vacation.

Allen
 

Thread Starter

abhimanyu143

Joined Aug 25, 2014
211
I have got a lot of good design ideas from the link pointed by Ian Rogers of ETO here

http://www.bigmessowires.com/2013/08/27/custom-4-bit-cpu-schematic-and-control/

The Architecture is here

View attachment 78625

And the complete schematics is here

View attachment 78626

From this I am going to split your 8-bit ROM data into two halves. 4 bits for instructions and the other 4 bits for Imm data for MOV a,#imm and MOV R1,#imm; OR upper 4 bits of the 12 bit address on the JMP instruction.....

So much for now until I return from my vacation.

Allen
ok I am trying to make that design on proteus software. I have few question.I am also searching . I can't place all component in one sheet. I have to add another sheet. how to connect component from different sheet. how to see different sheet in one paper.
 
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