Hello,

I have uploaded a Mealy-Type FSM for a Serial Adder (it is from the book "Fundamentals of Digital Logic with VHDL Design by Stephen Brown and Zvonko Vranesic, second edition, page 515). I cannot understand why will FSM will remain in the same state for input valuations 01 and 10. For example, if the input valuation is 01 then the sum will be 1. Shouldn't it move to the next state? because if the sum is 1 there has to be a carry as well. Thanks in advance.

 

An addition of 2 bits creates a carry only if the sum is greater than 1. The additions 0+0, 0+1, 1+0 don't create a carry. The additions 1+1 and 1+1+1 do create a carry.

If you examine the machine more carefully, you will see that it doesn't store the Sum of each bit pair. Its inputs are the 2 bits to be added, and its 1-bit ouptut is the Sum of those 2 bits.

State G is the state of "No Carry" and state H is the state of "Carry". So, let's start from G and take an example input.
00 will have a sum of 0 (displayed, not stored) and a carry of 0 (therefore we stay at G)
01 will have a sum of 1 and a carry of 0
11 will have a sum of 0 and a carry of 1 (therefore we jump to H)
10 will have a sum of 0 (1+carry) and a carry of 1 (therefore we stay on H)
11 will have a sum of 1 and a carry of 1 (1+1+1=11)
00 will have a sum of 1 and a carry of 0 (0+0+1=01, therefore we jump on G)

Is that clear?

 

Yes, I can see the logic behind this. So, to convert it to a Moore type, we would need two states for G and two states for H (G can be 0 or 1 and H can be 0 or 1).

Is is possible to refer to a book (preferably an ebook) that can explain this much better? The one that I have is very hard to follow.

 

In order to convert it to a Moore machine, you would need more states. Check this tutorial and come back with your questions.
http://forum.allaboutcircuits.com/showthread.php?t=44399