Hello guys..
I'm studying digital logic design basics this semester..and I have some questions that need logical answers.first,I want to ask about latches.How do they store a bit,is it stored in the feed back loop.Also,I did an experiment on LogicWorcks, I constructed an sr latch-type doesn't matter I guess-and I connected the output to a binary probe...after I had a value for the output.I disconnected the latch from the input switch...and I had an X at the probe.I did same thing to a flip flop but it stored the output..it didn't lose it.

The other thing is when I construct a latch or FF-whatever-whith out touching the outputs...what would I get for the outputs..(especially for jk flip flop whe n j=k=0 I would have the current state,but here is the problem...what is it?

I'm sorry I asked a lot of questions.But I really need answers because my head is spinning right now .

 

The simplest latch is two inverters: connect the output of A to the input of B, then the output of B to the input of A. If you assume the output of A to be either a 1 or a zero and follow it thru you will see it is a stable condition. Once set to some state it will stay that way.

Of course, in that example you have no way to SET either state, but it will be stable. You can build a practicable flip flop with two NOR or two NAND gates; the NOR needs positive pulses to set the state (normally inputs are low), then NAND needs negative pulses from normally high inputs.

It's called a "set-reset flip flop", a term that Google will provide you with lots of information, including the Wikipedia article. Note basic S-R flip flops need no clock.

The "current state" of a JK is whatever the flip flop state is when you clock it. The initial state when it powers up is not defined, you have to do something if you want a specific state.

That is one good reason most JK F/F's have SET and CLEAR inputs.

Finally, if you look at the schematic for a JK flip flop you will find at least one if not two set-reset flip flops.