NE555 problem

Thread Starter

old_owl

Joined May 3, 2009
10
I'm trying to make a very low frequency timer. I've seen from experience that the best way to do this is with high resistance and low capacitance because large capacitors leak. Just yesterday I was able to configure timers with periods of around one minute, however when either the R1 or R2 values reach a certain point, the output of the timer stays high indefinitely. I've taken the large resistors out and put in smaller ones and the timer has worked perfectly. Is there any particularly obvious (or maybe not so obvious) reason for this problem?
 

SgtWookie

Joined Jul 17, 2007
22,230
Post your circuit so that we can see what values you're using, and where.

Use the "Go Advanced" button, and on the next page click the "Manage Attachments" to upload an image of your schematic from your computer. .PNG files work well, because that format is not "lossy" like .JPG format.
 

SgtWookie

Joined Jul 17, 2007
22,230
You're probably using an electrolytic capacitor that has a leakage rate which is too high for the 1 Meg resistor to charge it up to 2/3 Vcc. This will prevent the 555 from oscillating.

[eta]
There is also a threshold current drawn by pin 6. This normally isn't of much consequence when using a low-leakage cap, until R1+R2 > 7 Meg.

You might try to re-form your electrolytic capacitor to improve it's leakage rate. This is done by charging the capacitor to it's rated voltage over a period of time (perhaps over several hours) through a 10k resistor. Measure the voltage across the 10k resistor to determine the leakage. 1v = 0.1mA leakage.
 
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Thread Starter

old_owl

Joined May 3, 2009
10
Thanks a lot for your help. I guess that would fall under the category of "obvious". I decided to use a ceramic capacitor to fix that problem.

However, this leads to another problem. Namely, the fact that the first pulse of the timer is 1.6 times longer than the others. Is there any convenient (i.e., no transistors) method to fix this?
 

SgtWookie

Joined Jul 17, 2007
22,230
Thanks a lot for your help. I guess that would fall under the category of "obvious".
It's really not that obvious. Many people don't really know that electrolytic caps have a fair amount of leakage current, and that increases with age. As I mentioned in the previous post, sometimes electrolytic caps can be reformed. However, if the leakage current doesn't decrease to an acceptable level, the cap must be replaced.

I decided to use a ceramic capacitor to fix that problem.
Well, ceramics are pretty low leakage, but also normally available in only very small values of capacitance (typically the picofarad range, some in nanofarads). Poly or mylar caps would work, and typically have much lower leakage.

However, this leads to another problem. Namely, the fact that the first pulse of the timer is 1.6 times longer than the others. Is there any convenient (i.e., no transistors) method to fix this?
Not so easy to solve. Before power is first applied to the circuit, the cap is completely discharged (0v). When power is applied, the cap charges to 2/3 Vcc which is the upper threshold. When the upper threshold is reached, the discharge cycle begins; it continues until the lower threshold is reached, which is 1/3 Vcc.

The lower threshold is not externally accessible. Pin 5 gives access to the upper threshold. You could lower the upper threshold which would also decrease the lower threshold, but as a consequence the output frequency would increase, and the 1st time period would still be longer than the 2nd and subsequent time periods.

If you want the first time period to be the same as the subsequent time periods, you'll have to figure out a way to pre-charge the timing cap to 1/3 Vcc.
 

tkng211

Joined Jan 4, 2008
65
However, this leads to another problem. Namely, the fact that the first pulse of the timer is 1.6 times longer than the others. Is there any convenient (i.e., no transistors) method to fix this?

You may use a capacitor to charge the timing capacitor and keep the first pulse timing close to that of the others
 

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SgtWookie

Joined Jul 17, 2007
22,230
Interesting idea, tkng211. It does work in simulation, and brings about more interesting possibilities, too.

If the timing cap is split into two capacitors so that 2/3 of the capacitance is to ground, and the other 1/3 to Vcc, the first pulse will have the same duration as the subsequent pulses.

If it's split the same way, but 2/3 of the capacitance is to Vcc, and the other 1/3 to ground, the first output pulse will be delayed by the off time; eg: the first output is low instead of high.
 
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